# US 12,112,202 B2 · Framework for application driven exploration and optimization of hardware engines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,202 B2 - Document ID: US12112202B2 - Status: Granted - Kind: B2 - Application number: 16/882,640 - Filed: 2020-05-25 - Published: 2020-11-26 - Granted: 2024-10-08 - Earliest claimed: 2019-05-25 - Assignees: Synopsys, Inc. - Applicants: Synopsys, Inc. - Inventors: Amit Garg; Amit Tara; Shripad Deshpande - Web page: https://patentgrep.com/patent/US12112202B2 ## CPC - G06F 9/5005: {to service a request} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/455: Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines - G06F 9/45533: {Hypervisors; Virtual machine monitors} - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 9/48: Program initiating; Program switching, e.g. by interrupt - G06F 9/4806: {Task transfer initiation or dispatching} - G06F 9/4843: {by program, e.g. task dispatcher, supervisor, operating system} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/50: Allocation of resources, e.g. of the central processing unit [CPU] - G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)} - G06F 9/5061: {Partitioning or combining of resources} - G06F 9/5066: {Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system and method for evaluating optimization of a hardware engine are described herein. In an example embodiment, a first operation of a desired application is performed using one or more hardware resources each associated with one or more task graphs of a plurality of task graphs. A first result is recorded from a first simulation based on a first task graph of the plurality of task graphs implemented using a first configuration of a first hardware resource associated with the first task graph. A second result is recorded from a second simulation based on a second task graph of the plurality of task graphs implemented using a second configuration of a second hardware resource associated with the second task graph. An interface is generated based on the first result and the second result for rendering by a display device. ## Claims ### Claim 1 A computer-implemented method comprising: generating, by a processor, a first task graph corresponding to an application software and defining a functionality so as to generate a first result, wherein the first task graph comprises a first plurality of tasks each configured to be implemented by a first configuration of a first hardware resource, wherein the first configuration includes firmware held in a non-volatile memory device; generating, by the processor, a second task graph corresponding to the application software and defining the functionality so as to generate a second result, wherein the second task graph comprises a second plurality of tasks each configured to be implemented by a second configuration of a second hardware resource, wherein the second configuration includes a hardware acceleration resource; and changing a code associated with the application software based on a comparison of the first result associated with the first configuration of the first hardware resource and the second result associated with the second configuration of the second hardware resource. ### Claim 2 (depends on 1) The method of claim 1, wherein the first task graph comprises a first input interface and a first output interface and the second task graph comprises a second input interface and a second output interface. ### Claim 3 (depends on 2) The method of claim 2, wherein the first input interface matches the second input interface and the first output interface matches the second output interface. ### Claim 4 (depends on 1) The method of claim 1, further comprising: encapsulating one or more of the first the hardware resource and the second hardware resource into a hardware engine; generating a hardware engine input interface and a hardware engine output interface for the hardware engine; and mapping one or more operations associated with the application software to the hardware engine. ### Claim 5 (depends on 1) The method of claim 1, further comprising changing a configuration of one or more of the first hardware resource and the second hardware resource based on the comparison of the first and second results. ### Claim 6 (depends on 5) The method of claim 5, wherein one or more of the first and second configurations comprises one or more configurable attributes. ### Claim 7 (depends on 6) The method of claim 6, wherein the one or more configurable attributes comprise one of core type, firmware designation, general purpose, special purpose, packet size, packet descriptor size, processing speed, operations-per-cycle, pipeline-depth, branch predictor, stochastic cache, or tightly coupled memory (TCM). ### Claim 8 (depends on 5) The method of claim 5, wherein at least one of the first hardware resource or the second hardware resource comprises a processing element and a memory. ### Claim 9 (depends on 8) The method of claim 8, wherein at least one of the first hardware resource or the second hardware resource further comprises one or more hardware resource interfaces. ### Claim 10 (depends on 1) The method of claim 1, wherein the interface comprises digital representations of one or more of utilization data, resource utilization data, performance data, cost data, area data, timing data, resource analysis trace data, execution sequence trace data, resource instance trace data. ### Claim 11 (depends on 4) The method of claim 4, further comprising: receiving a result from one or more of the first plurality of tasks of the first task graph, or the second plurality of tasks of the second task graph, or the operation associated with the application software via interaction signals. ### Claim 12 (depends on 1) The method of claim 1, further comprising: receiving a configuration associated with at least one of the first hardware resource or the second hardware resource via interaction signals from a computing device prior to the generation of the first result and the second result. ### Claim 13 (depends on 1) The method of claim 1, wherein the first result and the second result are performed concurrently. ### Claim 14 (depends on 1) The method of claim 1, wherein the comparison of the first result and the second result provides information indicative of one or more of dependency and resource allocation. ### Claim 15 (depends on 1) The method of claim 1 further comprising: enabling exploration of trade-offs between the implementation of the functionalities associated with the first task graph and the second task graph. ### Claim 16 (depends on 1) The method of claim 1, wherein the first task graph and the second task graphs are subsets of a set of task graphs available for selection to provide optimal performance of the application software. ### Claim 17 A system comprising a memory storing instructions and a processor, coupled with the memory and to execute the instructions, the instructions when executed causing the processor to: generate a first task graph corresponding to an application software and defining a functionality so as to generate a first result, wherein the first task graph comprises a first plurality of tasks each configured to be implemented by a first configuration of a first hardware resource, wherein the first configuration includes firmware held in a non-volatile memory; generate a second task graph corresponding to the application software and defining the functionality so as to generate a second result, wherein the second task graph comprises a second plurality of tasks each configured to be implemented by a second configuration of a second hardware resource, wherein the second configuration includes a hardware acceleration resource; and change a code associated with the application software based on a comparison of the first result associated with the first configuration of the first hardware resource and the second result associated with the second configuration of the second hardware. ### Claim 18 A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to: generate a first task graph corresponding to an application software and defining a functionality so as to generate a first result, wherein the first task graph comprises a first plurality of tasks each configured to be implemented by a first configuration of a first hardware resource, wherein the first configuration includes firmware held in a non-volatile memory device; generate a second task graph corresponding to the application software and defining the functionality so as to generate a second result, wherein the second task graph comprises a second plurality of tasks each configured to be implemented by a second configuration of a second hardware resource, wherein the second configuration includes a hardware acceleration resource; and change a code associated with the application software based on a comparison of the first result associated with the first configuration of the first hardware resource and the second result associated with the second configuration of the second hardware resource. ### Claim 19 (depends on 18) The non-transitory computer readable medium of claim 18 wherein the instructions further cause the processor to generate an input interface and an output interface for the first task graph.