# US 12,112,196 B2 · Real-time scheduling for a heterogeneous multi-core system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,196 B2 - Document ID: US12112196B2 - Status: Granted - Kind: B2 - Application number: 17/240,106 - Filed: 2021-04-26 - Published: 2022-10-27 - Granted: 2024-10-08 - Earliest claimed: 2021-04-26 - Assignees: GM Global Technology Operations LLC - Applicants: GM Global Technology Operations LLC - Inventors: Guy Drory; Gilboa Shveki - Web page: https://patentgrep.com/patent/US12112196B2 ## CPC - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/3867: {using instruction pipelines} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/544: {Buffers; Shared memory; Pipes} - G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A heterogeneous multi-core system that executes a real-time system for an automobile includes a plurality of system-on chips in electronic communication with one another. Each system-on-chip includes a plurality of central processing units (CPUs) arranged into a plurality of logical domains. The heterogeneous multi-core system also includes a plurality of scheduled tasks that are executed based on an execution pipeline and each execute a specific set of tasks for one of the logical domains. The plurality of scheduled tasks includes at least one offset scheduled task that is executed at an offset time and a reference scheduled task located at an execution stage upstream in the execution pipeline relative to the offset scheduled task. The reference scheduled task communicates data to the offset scheduled task and the offset time represents a period of time measured relative to the reference scheduled task. ## Claims ### Claim 1 A heterogeneous multi-core system that executes a real-time system for an automobile, the heterogeneous multi-core system comprising: a plurality of system-on chips in electronic communication with one another, wherein each system-on-chip includes a plurality of central processing units (CPUs) arranged into a plurality of logical domains; a plurality of scheduled tasks that are executed based on an execution pipeline and each execute a specific set of tasks for one of the logical domains, wherein the plurality of scheduled tasks includes: at least one offset scheduled task that is executed at an offset time, wherein the offset time for the at least one offset scheduled task is determined by selecting a predefined percentage of a total runtime of cases that are executed to completion; and a reference scheduled task located at an execution stage upstream in the execution pipeline relative to the offset scheduled task, wherein the reference scheduled task communicates data to the offset scheduled task and the offset time represents a period of time measured relative to the reference scheduled task, and wherein each stage of the execution pipeline of the real-time system includes a guaranteed latency that is based on the offset time of the at least one offset scheduled task. ### Claim 2 (depends on 1) The heterogeneous multi-core system of claim 1, wherein the execution pipeline includes a guaranteed end-to-end latency. ### Claim 3 (depends on 1) The heterogeneous multi-core system of claim 1, wherein each logical domain executes one or more scheduled tasks, and wherein each scheduled task executes based on a unique periodicity. ### Claim 4 (depends on 3) The heterogeneous multi-core system of claim 3, wherein each of the plurality of system-on-chips include a corresponding shared memory. ### Claim 5 (depends on 4) The heterogeneous multi-core system of claim 4, wherein a priority table indicating a runtime priority for each of the one or more scheduled tasks is stored in the shared memory. ### Claim 6 (depends on 5) The heterogeneous multi-core system of claim 5, wherein the runtime priority for each of the one or more scheduled tasks is determined based on the unique periodicity. ### Claim 7 (depends on 1) The heterogeneous multi-core system of claim 1, further comprising one or more synchronizers, wherein the one or more synchronizers synchronize two or more inputs having different periodicities together and transmit data from the two more inputs to one of the plurality of scheduled tasks. ### Claim 8 (depends on 7) The heterogeneous multi-core system of claim 7, wherein each of the one or more synchronizers includes a trigger. ### Claim 9 (depends on 8) The heterogeneous multi-core system of claim 8, wherein the trigger represents a software event that prompts a corresponding synchronizer to synchronize the two or more inputs together. ### Claim 10 (depends on 1) The heterogeneous multi-core system of claim 1, further comprising one or more synchronizers, wherein the one or more synchronizers changes a periodicity from a single input and transmits data from the single input to one of the plurality of scheduled tasks. ### Claim 11 (depends on 1) The heterogeneous multi-core system of claim 1, wherein each of the plurality of scheduled tasks include a unique periodicity. ### Claim 12 (depends on 1) The heterogeneous multi-core system of claim 1, wherein each system-on-chip further comprises one or more hardware accelerators that are shared between the CPUs. ### Claim 13 (depends on 1) The heterogeneous multi-core system of claim 1, wherein the (Original) real-time system is an advanced driving assistance system (ADAS). ### Claim 14 (depends on 1) The heterogeneous multi-core system of claim 1, wherein each CPU is allocated to one of the plurality of logical domains. ### Claim 15 A heterogeneous multi-core system that executes a real-time system for an automobile, the heterogeneous multi-core system comprising: a plurality of system-on chips in electronic communication with one another, wherein each system-on-chip includes a plurality of CPUs arranged into a plurality of logical domains, and wherein the real-time system is an advanced driving assistance system (ADAS); one or more synchronizers, wherein the one or more synchronizers synchronize two or more inputs having different periodicities together; and a plurality of scheduled tasks that are executed based on an execution pipeline and each execute a specific set of tasks for one of the logical domains, wherein the one or more synchronizers transmit data from the two more inputs to one of the plurality of scheduled tasks, and wherein the plurality of scheduled tasks includes: at least one offset scheduled task that is executed at an offset time, wherein the offset time for the at least one offset scheduled task is determined by selecting a predefined percentage of a total runtime of cases that are executed to completion; and a reference scheduled task located at an execution stage upstream in the execution pipeline relative to the offset scheduled task, wherein the reference scheduled task communicates data to the offset scheduled task and the offset time represents a period of time measured relative to the reference scheduled task, and wherein each stage of the execution pipeline of the real-time system includes a guaranteed latency that is based on the offset time of the at least one offset scheduled task. ### Claim 16 (depends on 15) The heterogeneous multi-core system of claim 15, wherein the execution pipeline includes a guaranteed end-to-end latency. ### Claim 17 (depends on 15) The heterogeneous multi-core system of claim 15, wherein each of the one or more synchronizers includes a trigger. ### Claim 18 (depends on 17) The heterogeneous multi-core system of claim 17, wherein the trigger represents a software event that prompts a corresponding synchronizer to synchronize the two or more inputs together. ### Claim 19 (depends on 15) The heterogeneous multi-core system of claim 15, wherein each logical domain executes one or more scheduled tasks, and wherein each scheduled task executes based on a unique periodicity. ### Claim 20 A heterogeneous multi-core system that executes a real-time system for an automobile, the heterogeneous multi-core system comprising: a plurality of system-on chips in electronic communication with one another, wherein each system-on-chip includes a plurality of CPUs arranged into a plurality of logical domains, and wherein the real-time system is an advanced driving assistance system (ADAS); one or more synchronizers; and a plurality of scheduled tasks that are executed based on an execution pipeline and each execute a specific set of tasks for one of the logical domains, wherein the one or more synchronizers changes a periodicity from a single input and transmits data from the single input to one of the plurality of scheduled tasks, and wherein the plurality of scheduled tasks includes: at least one offset scheduled task that is executed at an offset time, wherein the offset time for the at least one offset scheduled task is determined by selecting a predefined percentage of a total runtime of cases that are executed to completion; and a reference scheduled task located at an execution stage upstream in the execution pipeline relative to the offset scheduled task, wherein the reference scheduled task communicates data to the offset scheduled task and the offset time represents a period of time measured relative to the reference scheduled task, and wherein each stage of the execution pipeline of the real-time system includes a guaranteed latency that is based on the offset time of the at least one offset scheduled task.