# US 12,112,176 B1 · Selective firmware placement during initialization of compute systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,176 B1 - Document ID: US12112176B1 - Status: Granted - Kind: B1 - Application number: 18/184,518 - Filed: 2023-03-15 - Published: 2024-09-19 - Granted: 2024-10-08 - Earliest claimed: 2023-03-15 - Assignees: Quanta Computer Inc. - Applicants: Quanta Computer Inc. - Inventors: Yu-Han Lin - Web page: https://patentgrep.com/patent/US12112176B1 ## CPC - G06F 9/4403: {Processor initialisation} - G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An example computer-implemented method is for initializing a compute system. The computer-implemented method includes causing a cache to be initialized in a central processing unit (CPU) of the compute system in response to basic input/output system (BIOS) code being executed directly from flash memory. Moreover, a communication path is initialized, the communication path extending between the CPU and memory corresponding to a baseboard management controller (BMC) of the compute system. BIOS firmware is copied from the BMC memory to the CPU cache, and the BIOS firmware is initiated from the CPU cache. The computer-implemented method includes causing a memory controller of the CPU to be initialized, in addition to causing a portion of the BIOS firmware to be copied from the CPU cache to memory corresponding to the CPU. Furthermore, a portion of the BIOS firmware is initiated from the CPU memory. ## Claims ### Claim 1 A computer-implemented method for initializing a compute system, the computer-implemented method comprising: in response to basic input/output system (BIOS) code being executed directly from flash memory, causing a cache to be initialized in a central processing unit (CPU) of the compute system; causing a communication path to be initialized, the communication path extending between the CPU and memory corresponding to a baseboard management controller (BMC) of the compute system; causing BIOS firmware to be copied from the BMC memory to the CPU cache; causing the BIOS firmware to be initiated from the CPU cache; causing a memory controller of the CPU to be initialized; causing a portion of the BIOS firmware to be copied from the CPU cache to memory corresponding to the CPU; and causing the portion of the BIOS firmware to be initiated from the CPU memory. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, wherein causing the BIOS firmware to be initiated from the CPU cache includes calling to a pre-EFI initialization (PEI) entry point in the BIOS firmware in the CPU cache, thereby initiating a PEI phase of initializing the compute system. ### Claim 3 (depends on 2) The computer-implemented method of claim 2, further comprising calling to PEI modules (PEIMs) in the CPU cache, wherein the PEIMs are used to initialize the memory controller of the CPU. ### Claim 4 (depends on 1) The computer-implemented method of claim 1, wherein the BMC memory includes random access memory (RAM). ### Claim 5 (depends on 1) The computer-implemented method of claim 1, wherein the communication path extends between the CPU and a shared portion of the BMC memory, the shared portion of the BMC memory being accessible to the CPU and the BMC. ### Claim 6 (depends on 1) The computer-implemented method of claim 1, further comprising: calling to pre-EFI initialization modules (PEIMs) in the CPU memory; causing BIOS firmware to be copied from the BMC memory to the CPU memory; and causing the BIOS firmware to be initiated from the CPU memory. ### Claim 7 (depends on 6) The computer-implemented method of claim 6, wherein the BIOS firmware copied from the BMC memory to the CPU memory includes driver execution environment (DXE) foundation code, wherein causing the BIOS firmware to be initiated from the CPU memory includes calling to a DXE entry point in the DXE foundation code, thereby initiating a DXE phase of initializing the compute system. ### Claim 8 (depends on 1) The computer-implemented method of claim 1, wherein the flash memory includes serial peripheral interface NOR flash memory. ### Claim 9 A computer program product for initializing a compute system, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a processor to cause the processor to: in response to basic input/output system (BIOS) code being executed directly from flash memory, cause, by the processor, a cache to be initialized in a central processing unit (CPU) of the compute system; cause, by the processor, a communication path to be initialized, the communication path extending between the CPU and memory corresponding to a baseboard management controller (BMC) of the compute system; cause, by the processor, BIOS firmware to be copied from the BMC memory to the CPU cache; cause, by the processor, the BIOS firmware to be initiated from the CPU cache; causing a memory controller of the CPU to be initialized; cause, by the processor, a portion of the BIOS firmware to be copied from the CPU cache to memory corresponding to the CPU; and cause, by the processor, the portion of the BIOS firmware to be initiated from the CPU memory. ### Claim 10 (depends on 9) The computer program product of claim 9, wherein causing the BIOS firmware to be initiated from the CPU cache includes calling to a pre-EFI initialization (PEI) entry point in the BIOS firmware in the CPU cache, thereby initiating a PEI phase of initializing the compute system. ### Claim 11 (depends on 10) The computer program product of claim 10, wherein the program instructions are further readable and/or executable by the processor to cause the processor to call, by the processor, to PEI modules (PEIMs) in the CPU cache, wherein the PEIMs are used to initialize the memory controller of the CPU. ### Claim 12 (depends on 9) The computer program product of claim 9, wherein the BMC memory includes random access memory (RAM). ### Claim 13 (depends on 9) The computer program product of claim 9, wherein the communication path extends between the CPU and a shared portion of the BMC memory, the shared portion of the BMC memory being accessible to the CPU and the BMC. ### Claim 14 (depends on 9) The computer program product of claim 9, wherein the program instructions are further readable and/or executable by the processor to cause the processor to: call, by the processor, to pre-EFI initialization modules (PEIMs) in the CPU memory; cause, by the processor, BIOS firmware to be copied from the BMC memory to the CPU memory; and cause, by the processor, the BIOS firmware to be initiated from the CPU memory. ### Claim 15 (depends on 14) The computer program product of claim 14, wherein the BIOS firmware copied from the BMC memory to the CPU memory includes driver execution environment (DXE) foundation code, wherein causing the BIOS firmware to be initiated from the CPU memory includes calling to a DXE entry point in the DXE foundation code, thereby initiating a DXE phase of initializing the compute system. ### Claim 16 (depends on 9) The computer program product of claim 9, wherein the flash memory includes serial peripheral interface NOR flash memory. ### Claim 17 A compute system, comprising: flash memory; a central processing unit (CPU); a baseboard management controller (BMC); a processor; and logic integrated with and/or executable by the processor, the logic being configured to: in response to basic input/output system (BIOS) code being executed directly from the flash memory, cause, by the processor, a cache to be initialized in the CPU; cause, by the processor, a communication path to be initialized, the communication path extending between the CPU and memory corresponding to the BMC; cause, by the processor, BIOS firmware to be copied from the BMC memory to the CPU cache; cause, by the processor, the BIOS firmware to be initiated from the CPU cache; causing a memory controller of the CPU to be initialized; cause, by the processor, a portion of the BIOS firmware to be copied from the CPU cache to memory corresponding to the CPU; and cause, by the processor, the portion of the BIOS firmware to be initiated from the CPU memory. ### Claim 18 (depends on 17) The compute system of claim 17, wherein the logic is further configured to: call, by the processor, to pre-EFI initialization modules (PEIMs) in the CPU memory; cause, by the processor, BIOS firmware to be copied from the BMC memory to the CPU memory; and cause, by the processor, the BIOS firmware to be initiated from the CPU memory. ### Claim 19 (depends on 18) The compute system of claim 18, wherein the BIOS firmware copied from the BMC memory to the CPU memory includes driver execution environment (DXE) foundation code, wherein causing the BIOS firmware to be initiated from the CPU memory includes calling to a DXE entry point in the DXE foundation code, thereby initiating a DXE phase of initializing the compute system. ### Claim 20 (depends on 17) The compute system of claim 17, wherein the flash memory is separated from the CPU and BMC by a multiplexer, wherein the communication path extends between the CPU and a shared portion of the BMC memory, the shared portion of the BMC memory being accessible to the CPU and the BMC.