# US 12,112,171 B2 · Loop support extensions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,171 B2 - Document ID: US12112171B2 - Status: Granted - Kind: B2 - Application number: 17/134,367 - Filed: 2020-12-26 - Published: 2022-03-31 - Granted: 2024-10-08 - Earliest claimed: 2020-09-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Anant Nori; Shankar Balachandran; Sreenivas Subramoney; Joydeep Rakshit; Vedvyas Shanbhogue; Avishaii Abuhatzera; Belliappa Kuttanna - Web page: https://patentgrep.com/patent/US12112171B2 ## CPC - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/30065: {Loop control instructions; iterative instructions, e.g. LOOP, REPEAT} - G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP} - G06F 9/30181: {Instruction operation extension or modification} - G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode} - G06F 9/325: {for loops, e.g. loop detection or loop counter} - G06F 9/3455: {using stride} - G06F 9/381: {Loop buffering} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques for processing loops are described. An exemplary apparatus at least includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions; and execution circuitry to perform the operation as indicated by the opcode. ## Claims ### Claim 1 An apparatus comprising: decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be: placed into code storage after being decoded, unrolled and scheduled from the code storage using an unroll scheduler, and placed into one or more issue queues for execution; and the execution circuitry to perform the operation as indicated by the opcode. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the metadata generated is to include at least one of a loop count, a stride value, and a base address. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be duplicated in the one or more issue queues such that there is an instance per loop iteration. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the code storage is a register file. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to utilize a bit in a prefix to identify them as instructions that are to use metadata generated by ones of the plurality of configuration instructions. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be tagged by the decoder to identify them as instructions that are to use metadata generated by ones of the plurality of configuration instructions. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be identified by the decoder by an opcode. ### Claim 8 A non-transitory machine-readable medium storing at least one instruction which when processed by a processor is to cause the processor to perform a method comprising: decoding a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be: placed into code storage after being decoded, unrolled and scheduled from the code storage using an unroll scheduler, and placed into one or more issue queues for execution; and executing the decoded instruction to perform the operation as indicated by the opcode. ### Claim 9 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the metadata generated is to include at least one of a loop count, a stride value, and a base address. ### Claim 10 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be duplicated in the one or more issue queues such that there is an instance per loop iteration. ### Claim 11 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the code storage is a register file. ### Claim 12 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to utilize a bit in a prefix to identify them as instructions that are to use metadata generated by ones of the plurality of configuration instructions. ### Claim 13 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be tagged by the decoder to identify them as instructions that are to use metadata generated by ones of the plurality of configuration instructions. ### Claim 14 (depends on 8) The non-transitory machine-readable medium of claim 8, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be identified by the decoder by an opcode. ### Claim 15 A system apparatus comprising: memory to store instructions; a processor coupled to the memory, the processor comprising: decoder circuitry to decode a single instruction of the stored instructions, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions, wherein the instructions that are to use metadata generated by ones of the plurality of configuration instructions are to be: placed into code storage after being decoded, unrolled and scheduled from the code storage using an unroll scheduler, and placed into one or more issue queues for execution; and the execution circuitry to perform the operation as indicated by the opcode. ### Claim 16 (depends on 15) The system of claim 15, wherein the metadata generated is to include at least one of a loop count, a stride value, and a base address. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein the code storage is a register file.