# US 12,112,167 B2 · Matrix data scatter and gather between rows and irregularly spaced memory locations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,167 B2 - Document ID: US12112167B2 - Status: Granted - Kind: B2 - Application number: 16/914,321 - Filed: 2020-06-27 - Published: 2021-12-30 - Granted: 2024-10-08 - Earliest claimed: 2020-06-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Christopher J. Hughes; Alexander F. Heinecke; Robert Valentine; Menachem Adelman; Evangelos Georganas; Mark J. Charney; Nikita A. Shustrov; Sara Baghsorkhi - Web page: https://patentgrep.com/patent/US12112167B2 ## CPC - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30098: {Register arrangements} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments for gathering and scattering matrix data by row are disclosed. In an embodiment, a processor includes a storage matrix, a decoder, and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode and a first operand field to specify a set of irregularly spaced memory locations. The execution circuitry is to, in response to the decoded instruction, calculate a set of addresses corresponding to the set of irregularly spaced memory locations and transfer a set of rows of data between the storage and the set of irregularly spaced memory locations. ## Claims ### Claim 1 A processor comprising: storage for a matrix; a decoder to decode an instruction having a format including an opcode field to specify an opcode and a first operand field to specify a set of irregularly spaced memory locations by specifying a set of indices, the set of indices including at least one index having a reserved value; and execution circuitry to, in response to the decoded instruction, calculate a set of addresses corresponding to the set of irregularly spaced memory locations and transfer a set of rows of data between the storage and the set of irregularly spaced memory locations, wherein the reserved value is to indicate that a corresponding row is to be skipped or zeroed. ### Claim 2 (depends on 1) The processor of claim 1, wherein the first operand field is to specify the set of indices by specifying a register to store an address of a first index in the set of indices. ### Claim 3 (depends on 1) The processor of claim 1, wherein the execution circuitry is to calculate the set of addresses by adding each of the set of indices to a beginning memory address. ### Claim 4 (depends on 3) The processor of claim 3, wherein the first operand field is also to specify the beginning address or a base address with which the execution circuitry is to calculate the beginning address. ### Claim 5 (depends on 1) The processor of claim 1, wherein the format is also to include a second operand field to specify a register as the storage for the matrix. ### Claim 6 (depends on 1) The processor of claim 1, wherein the instruction is a row gather instruction and the execution circuitry, in response to the instruction, is to load the set of rows of data to the storage from the set of irregularly spaced memory locations. ### Claim 7 (depends on 1) The processor of claim 1, wherein the instruction is a row scatter instruction and the execution circuitry, in response to the instruction, is to store the set of rows of data from the storage to the set of irregularly spaced memory locations. ### Claim 8 A method comprising: decoding an instruction having a format including an opcode field to specify an opcode and a first operand field to specify a set of irregularly spaced memory locations by specifying a set of indices, the set of indices including at least one index having a reserved value; and executing the decoded instruction, wherein executing includes calculating a set of addresses corresponding to the set of irregularly spaced memory locations and transferring a set of rows of data between storage for a matrix and the set of irregularly spaced memory locations, wherein the reserved value is to indicate that a corresponding row is to be skipped or zeroed. ### Claim 9 (depends on 8) The method of claim 8, wherein calculating the set of addresses includes adding each of the set of indices to a beginning memory address. ### Claim 10 (depends on 8) The method of claim 8, wherein the format is also to include a second operand field to specify a register as the storage for the matrix. ### Claim 11 (depends on 8) The method of claim 8, wherein the instruction is a row gather instruction and executing includes loading the rows of data to the storage from the set of irregularly spaced memory locations. ### Claim 12 (depends on 8) The method of claim 8, wherein the instruction is a row scatter instruction and executing includes storing the rows of data from the storage to the set of irregularly spaced memory locations. ### Claim 13 A non-transitory machine-readable medium containing instructions, when executed by a processor, to cause the processor to respond by: decoding an instruction having a format including an opcode field to specify an opcode and a first operand field to specify a set of irregularly spaced memory locations by specifying a set of indices, the set of indices including at least one index having a reserved value; and executing the decoded instruction, wherein executing includes calculating a set of addresses corresponding to the set of irregularly spaced memory locations and transferring a set of rows of data between storage for a matrix and the set of irregularly spaced memory locations, wherein the reserved value is to indicate that a corresponding row is to be skipped or zeroed. ### Claim 14 (depends on 13) The non-transitory machine-readable medium of claim 13, wherein calculating the set of addresses includes adding each of the set of indices to a beginning memory address. ### Claim 15 (depends on 13) The non-transitory machine-readable medium of claim 13, wherein the format is also to include a second operand field to specify a register as the storage for the matrix. ### Claim 16 (depends on 13) The non-transitory machine-readable medium of claim 13, wherein the instruction is a row gather instruction and executing includes loading the set of rows of data to the storage from the set of irregularly spaced memory locations. ### Claim 17 (depends on 13) The non-transitory machine-readable medium of claim 13, wherein the instruction is a row scatter instruction and executing includes storing the set of rows of data from the storage to the set of irregularly spaced memory locations.