# US 12,112,163 B2 · Memory interface > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,163 B2 - Document ID: US12112163B2 - Status: Granted - Kind: B2 - Application number: 17/726,224 - Filed: 2022-04-21 - Published: 2023-06-08 - Granted: 2024-10-08 - Earliest claimed: 2021-12-03 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Hiroki Noguchi; Yih Wang - Web page: https://patentgrep.com/patent/US12112163B2 ## CPC - G06F 9/3001: {Arithmetic instructions} - G06F 3/0611: {in relation to response time} - G06F 3/0658: {Controller construction arrangements} - G06F 3/0673: {Single storage device} - G06F 7/575: Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory interface circuit includes an instruction decoder configured to receive an instruction from a processor to generate a corresponding control code. An execution circuit is configured to receive the control code from the instruction decoder and access a memory and generate an arithmetic result according to the control code. ## Claims ### Claim 1 A memory interface circuit, comprising: an instruction decoder configured to receive an instruction from a processor to generate a corresponding control code; and an execution circuit including an arithmetic-logic unit (ALU), wherein the execution circuit is configured to: receive the control code from the instruction decoder; access a memory; retrieve data stored in the memory; and generate an arithmetic result according to the control code based on the retrieved data; wherein the plurality of control codes includes a read control code, and wherein the execution circuit includes a read multiplexer (MUX) having a first input terminal connected to a read data input terminal, a second input terminal connected to receive the arithmetic result, a control terminal connected to receive the read control code, and a data output terminal, wherein the read MUX is configured to output the one of the retrieved data or the arithmetic result in response to the read control code; wherein the ALU includes: a first data input terminal; a second data input terminal; a control terminal, wherein the plurality of control codes includes a command code received by the control terminal of the ALU; and an output terminal configured to provide the generated arithmetic result; and wherein the execution circuit includes: a first register having an output terminal connected to the first data input terminal of the ALU; and a second register having an output terminal connected to the second data input terminal of the ALU; a first input data MUX having an output terminal connected to an input terminal of the first register; a second input data MUX having an output terminal connected to an input terminal of the second register; wherein the first input data MUX and the second input data MUX each include: a first input terminal connected to the write data input terminal; a second input terminal connected to the output terminal of the ALU; a third input terminal connected to the read data input terminal; a fourth input terminal, wherein the fourth input terminal of the first input data MUX is connected to the output terminal of the first register, and the fourth input terminal of the second input data MUX is connected to the output terminal of the second register; and a control terminal, wherein the plurality of control codes includes a first data select code received by the control terminal of the first input data MUX, and a second data select code received by the control terminal of the second input data MUX. ### Claim 2 (depends on 1) The interface circuit of claim 1, wherein the instruction received by the instruction decoder include a command and a memory address. ### Claim 3 (depends on 2) The interface circuit of claim 2, wherein the execution circuit is configured to retrieve the data from the memory based on the received memory address. ### Claim 4 (depends on 3) The interface circuit of claim 3, wherein the execution circuit is configured to selectively output one of the retrieved data or the arithmetic result. ### Claim 5 (depends on 4) The interface circuit of claim 4, wherein the control code includes a write control code, and wherein the execution circuit includes a write MUX having a first input terminal, a second input terminal, a control terminal and a data output terminal, the first input terminal connected to receive the arithmetic result, the second input terminal connected to receive input data, the control terminal connected to receive the write control code, and the data output terminal configured to output one of the received data or the arithmetic result to the memory in response to the write control code. ### Claim 6 A computing device, comprising: a processor; a memory; an address decoder connected between the processor and the memory, and configured to receive a memory address from the processor, decode the memory address, and output an address command to the memory; an instruction decoder connected between the processor and the memory, and configured to receive an instruction from the processor, decode the instruction, and output a command to the memory, the instruction decoder further configured to output a plurality of control codes based on the received instruction; and an execution circuit having an arithmetic-logic unit (ALU), a data output terminal connected to the processor, a write data input terminal configured to receive input data, and a read data input terminal configured to receive data retrieved from the memory based on the address command, wherein the execution circuit is configured to provide one of an arithmetic result or the data retrieved from the memory at the data output terminal based on the plurality of control codes; and wherein the plurality of control codes includes a read control code, and wherein the execution circuit includes a read multiplexer (MUX) having a first input terminal connected to the read data input terminal, a second input terminal connected to receive the arithmetic result, a control terminal connected to receive the read control code, and the data output terminal, wherein the read MUX is configured to output the one of the retrieved data or the arithmetic result in response to the read control code; wherein the ALU includes: a first data input terminal; a second data input terminal; a control terminal, wherein the plurality of control codes includes a command code received by the control terminal of the ALU; and an output terminal configured to provide the generated arithmetic result; and wherein the execution circuit includes: a first register having an output terminal connected to the first data input terminal of the ALU; and a second register having an output terminal connected to the second data input terminal of the ALU; a first input data MUX having an output terminal connected to an input terminal of the first register; a second input data MUX having an output terminal connected to an input terminal of the second register; wherein the first input data MUX and the second input data MUX each include: a first input terminal connected to the write data input terminal; a second input terminal connected to the output terminal of the ALU; a third input terminal connected to the read data input terminal; a fourth input terminal, wherein the fourth input terminal of the first input data MUX is connected to the output terminal of the first register, and the fourth input terminal of the second input data MUX is connected to the output terminal of the second register; and a control terminal, wherein the plurality of control codes includes a first data select code received by the control terminal of the first input data MUX, and a second data select code received by the control terminal of the second input data MUX. ### Claim 7 (depends on 6) The device of claim 6, further comprising a cache memory connected between the processor and the execution circuit. ### Claim 8 (depends on 7) The device of claim 7, wherein the cache memory is configured to receive data from the data output terminal of the execution circuit. ### Claim 9 (depends on 6) The device of claim 6, wherein the plurality of control codes includes a write control code; and wherein the execution circuit includes a write MUX having a first input terminal connected the output terminal of the ALU, a second input terminal connected to the write data input terminal, and a control terminal connected to receive the write control code. ### Claim 10 A method, comprising: receiving an instruction from a processor by an instruction decoder; outputting a memory address command based on the instruction to a memory by the instruction decoder; outputting a control code to an execution circuit connected to the memory, wherein the control code includes a read control code; receiving data read from the memory by the execution circuit based on the memory address command; generating an arithmetic result by an arithmetic-logic unit (ALU) of the execution circuit based on the control code and the data read from the memory; and outputting the arithmetic result by the ALU; wherein the execution circuit includes a read multiplexer (MUX) having a first input terminal connected to the read data input terminal, a second input terminal connected to receive the arithmetic result, a control terminal connected to receive the read control code, and a data output terminal, wherein the read MUX is configured to output the one of the retrieved data or the arithmetic result in response to the read control code; and wherein the ALU includes: a first data input terminal; a second data input terminal; a control terminal, wherein the plurality of control codes includes a command code received by the control terminal of the ALU; and an output terminal configured to provide the generated arithmetic result; and wherein the execution circuit includes: a first register having an output terminal connected to the first data input terminal of the ALU; and a second register having an output terminal connected to the second data input terminal of the ALU; a first input data MUX having an output terminal connected to an input terminal of the first register; a second input data MUX having an output terminal connected to an input terminal of the second register; wherein the first input data MUX and the second input data MUX each include: a first input terminal connected to the write data input terminal; a second input terminal connected to the output terminal of the ALU; a third input terminal connected to the read data input terminal; a fourth input terminal, wherein the fourth input terminal of the first input data MUX is connected to the output terminal of the first register, and the fourth input terminal of the second input data MUX is connected to the output terminal of the second register; and a control terminal, wherein the plurality of control codes includes a first data select code received by the control terminal of the first input data MUX, and a second data select code received by the control terminal of the second input data MUX. ### Claim 11 (depends on 10) The method of claim 10, wherein the arithmetic result is output to the processor. ### Claim 12 (depends on 10) The method of claim 10, wherein the arithmetic result is further based on data received from the processor, and wherein the arithmetic result is written to the memory based on the memory address command. ### Claim 13 (depends on 1) The interface circuit of claim 1, wherein the memory is an SRAM memory. ### Claim 14 (depends on 5) The interface circuit of claim 5, wherein the instruction decoder includes a first output terminal configured to output the read control code. ### Claim 15 (depends on 14) The interface circuit of claim 14, wherein the instruction decoder includes a second output terminal configured to output the first data select code. ### Claim 16 (depends on 15) The interface circuit of claim 15, wherein the instruction decoder includes a third output terminal configured to output the second data select code. ### Claim 17 (depends on 16) The interface circuit of claim 16, wherein the instruction decoder includes a fourth output terminal configured to output the write control code. ### Claim 18 (depends on 17) The interface circuit of claim 17, wherein the instruction decoder includes a fifth output terminal configured to output the command code. ### Claim 19 (depends on 7) The device of claim 7, wherein the cache memory includes an L1 cache, an L2 cache and an L3 cache. ### Claim 20 (depends on 6) The device of claim 6, wherein the memory is an SRAM memory.