# US 12,112,117 B2 · Method of manufacturing a semiconductor device including PG-aligned cells

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- Number: US 12,112,117 B2
- Document ID: US12112117B2
- Status: Granted
- Kind: B2
- Application number: 18/308,090
- Filed: 2023-04-27
- Published: 2023-08-31
- Granted: 2024-10-08
- Earliest claimed: 2017-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hiranmay Biswas; Chung-Hsing Wang; Kuo-Nan Yang
- Web page: https://patentgrep.com/patent/US12112117B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/36: Circuit design at the analogue level
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- H10D 84/907: {CMOS gate arrays}
- H10D 89/10: Integrated device layouts
- H10D 84/975: {Wiring regions or routing}
- H10D 84/981: {Power supply lines}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a semiconductor device includes forming a set of cells; forming a PG layer, including forming a first metallization layer including forming first conductor portions and second conductor portions, corresponding ones of the first conductor portions being arranged in first pairs; corresponding ones of the second conductor portions being arranged in second pairs; the cells being arranged to overlap at least one of the first and second conductor portions of the first metallization layer relative to the first direction; and forming a second metallization layer over the first metallization layer, the second metallization layer including forming third conductor portions and fourth conductor portions, the cells being arranged in a repeating relationship that each cell overlaps, an intersection of a corresponding one of the first or second pairs with at least a corresponding one of the third conductor portions or a corresponding one of the fourth conductor portions.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a set of cells wherein each cell is lacking input terminals and output terminals including:
forming a power-grid (PG) layer above the set of cells, including:
forming a first metallization layer including:
forming first conductor portions and second conductor portions which provide correspondingly a power-supply voltage and a reference voltage, and have long axes oriented substantially parallel to a first direction, wherein:
corresponding ones of the first conductor portions of the first metallization layer being arranged in first pairs;
corresponding ones of the second conductor portions of the first metallization layer being arranged in second pairs; and
the cells being arranged to overlap at least one of the first and second conductor portions of the first metallization layer relative to the first direction; and
forming a second metallization layer over the first metallization layer, the second metallization layer including:
forming third conductor portions and fourth conductor portions which provide correspondingly the power-supply voltage and the reference voltage and have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction, wherein:
the cells being arranged in a repeating relationship that each cell overlaps, relative to the first direction and the second direction, an intersection of (A) a corresponding one of the first or second pairs with (B) at least a corresponding one of the third conductor portions or a corresponding one of the fourth conductor portions.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the set of cells wherein each cell is lacking the input terminals and output terminals includes:
forming the set of cells wherein the cells include tap cells.

### Claim 3 (depends on 2)

The method of claim 2, wherein the forming the set of cells wherein each cell is lacking the input terminals and output terminals includes:
forming the set of cells wherein the cells further include decoupling capacitor (DCAP) cells.

### Claim 4 (depends on 2)

The method of claim 2, wherein the forming the set of cells wherein each cell is lacking the input terminals and output terminals includes:
forming the set of cells wherein the cells further include filler cells.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming the set of cells wherein each cell is lacking the input terminals and output terminals includes:
forming the set of cells wherein centers of the cells substantially align with centers of the corresponding first or second pairs.

### Claim 6 (depends on 1)

The method of claim 1, wherein the forming the PG layer further includes:
forming the third conductor portions and fourth conductor portions wherein corresponding ones of the third and fourth conductor portions are arranged into third pairs; and
the forming the set of cells wherein each cell is lacking the input terminals and output terminals includes:
forming the set of cells wherein each cell is symmetrically arranged with respect to the intersection of (A) the corresponding one of the first or second pairs with (B) a corresponding one of the third pairs.

### Claim 7 (depends on 6)

The method of claim 6, wherein the forming the set of cells wherein each cell is lacking the input terminals and output terminals includes:
forming the set of cells wherein, according to the repeating relationship of the cells, each cell is arranged symmetrically with respect to the intersection of (A) the corresponding one of the first or second pairs with (B) the corresponding one of the third pairs.

### Claim 8

A method of manufacturing a semiconductor device, comprising:
forming a set of cells wherein each cell is a monostate cell lacking input terminals and output terminals including:
forming a power-grid (PG) layer above the set of cells, including:
forming first conductor portions which provide correspondingly a power-supply voltage and a reference voltage, and have long axes oriented substantially parallel to a first direction, wherein:
corresponding ones of the first conductor portions of the PG layer being arranged in first pairs; and
the cells being arranged to overlap at least one of the first conductor portions of the PG layer relative to the first direction; and
forming a first metallization layer over the PG layer, the first metallization layer including:
forming second conductor portions which provide correspondingly the power-supply voltage and the reference voltage and have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction, wherein:
the cells being arranged in a repeating relationship that each cell symmetrically overlaps, relative to the first direction and the second direction, an intersection of (A) a corresponding one of the first conductor portions with (B) a corresponding one of the second conductor portions.

### Claim 9 (depends on 8)

The method of claim 8, wherein the forming the set of monostate cells wherein each cell is lacking the input terminals and output terminals includes:
forming the set of monostate cells where, according to the repeating relationship of the cells, centers of the cells are arranged to be substantially aligned with centers of corresponding first pairs.

### Claim 10 (depends on 9)

The method of claim 9, wherein the forming the second conductor portions includes:
forming corresponding ones of the second conductor portions of the first metallization layer arranged in second pairs; and
wherein the forming the set of monostate cells wherein each cell is lacking the input terminals and output terminals includes:
forming the monostate set of cells wherein according to the repeating relationship of the cells, each cell is arranged to overlap an intersection of (A) a corresponding one of the first pairs with (B) a corresponding one of the second pairs.

### Claim 11 (depends on 8)

The method of claim 8, wherein the forming the monostate set of cells wherein each cell is lacking the input terminals and output terminals include:
forming the monostate set of cells wherein the cells further include filler cells.

### Claim 12 (depends on 8)

The method of claim 8, wherein the forming the monostate set of cells wherein each cell is lacking the input terminals and output terminals include:
forming the monostate set of cells wherein the cells further include one or more of decoupling capacitor (DCAP) cells or filler cells.

### Claim 13 (depends on 8)

The method of claim 8, wherein the forming the monostate set of cells wherein each cell is lacking the input terminals and output terminals includes:
forming the monostate set of cells wherein the cells include tap cells.

### Claim 14 (depends on 8)

The method of claim 8, wherein the forming the monostate set of cells wherein each cell is lacking the input terminals and output terminals includes:
forming the monostate set of cells wherein centers of the cells substantially align with centers of the corresponding first or second pairs.

### Claim 15

A method of manufacturing a semiconductor device, comprising:
forming a set of cells wherein each cell is a monostate cell and lacking input terminals and output terminals including:
forming a power-grid (PG) layer above the set of cells, including:
forming a first metallization layer including:
forming first conductor portions and second conductor portions which are configured to provide correspondingly a power-supply voltage and a reference voltage, and have long axes oriented substantially parallel to a first direction, wherein:
corresponding ones of the first conductor portions of the first metallization layer being arranged in first pairs;
corresponding ones of the second conductor portions of the first metallization layer being arranged in second pairs; and
the cells being arranged to overlap at least one of the first and second conductor portions of the first metallization layer relative to the first direction; and
forming a second metallization layer over the first metallization layer, the second metallization layer including:
forming third conductor portions and fourth conductor portions which are configured to provide correspondingly the power-supply voltage and the reference voltage and have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction, wherein:
the cells being arranged in a repeating relationship that each cell overlaps, relative to the first direction and the second direction, an intersection of (A) a corresponding one of the first or second pairs with (B) at least a corresponding one of the third conductor portions or a corresponding one of the fourth conductor portions.

### Claim 16 (depends on 15)

The method of claim 15, wherein the forming the set of cells includes:
forming the set of cells wherein centers of the cells substantially align with centers of the corresponding first or second pairs.

### Claim 17 (depends on 15)

The method of claim 15, wherein the forming the set of cells includes:
forming the set of cells wherein the cells further include decoupling capacitor (DCAP) cells.

### Claim 18 (depends on 15)

The method of claim 15, wherein the forming the PG layer further includes:
forming the third conductor portions and fourth conductor portions wherein the corresponding ones of the third and fourth conductor portions are arranged into third pairs; and
the forming the set of cells includes:
forming the set of cells wherein each cell is symmetrically arranged with respect to the intersection of (A) the corresponding one of the first or second pairs with (B) a corresponding one of the third pairs.

### Claim 19 (depends on 18)

The method of claim 18, wherein the forming the set of cells includes:
forming the set of cells wherein, according to the repeating relationship of the cells, each cell is arranged symmetrically with respect to the intersection of (A) the corresponding one of the first or second pairs with (B) the corresponding one of the third pairs.

### Claim 20 (depends on 15)

The method of claim 15, wherein the forming the set of cells includes:
forming the set of cells wherein the cells further include filler cells.