# US 12,112,111 B1 · Method for analyzing static analog integrated circuit layout

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- Number: US 12,112,111 B1
- Document ID: US12112111B1
- Status: Granted
- Kind: B1
- Application number: 18/664,330
- Filed: 2024-05-15
- Granted: 2024-10-08
- Earliest claimed: 2023-05-15
- Assignees: Bayes Electronics Technology Co., Ltd; Tessersoft Co., Ltd
- Applicants: Bayes Electronics Technology Co., Ltd; Tessersoft Co., Ltd
- Inventors: Gang Fang; Wei Dong; Jiadong Gu; Zhenxin Zhao
- Web page: https://patentgrep.com/patent/US12112111B1

## CPC

- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- Y02E 60/00: Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

## Abstract

In a method for analyzing a static analog integrated circuit layout, corresponding simulation netlists are generated from an integrated circuit layout by parasitic parameter extraction, and device-node hypergraph or graph structures reflecting a circuit topological structure are generated from the simulation netlists. Then, characteristics of RC local networks between ports of individual device groups to be matched are analyzed. An independent source current is provided at i-ports of the RC networks, AC analysis is performed on the RC local networks to acquire impedance values of j-ports at different frequencies, and then a circuit mismatch condition is determined by comparing the impedance values of the individual RC local networks. The method automatically analyzes the analog integrated circuit layout to allow automatic analysis and determination of characteristic differences between a layout and a schematic design, improving the reliability of circuit mismatch examination and the efficiency of layout design.

## Claims

### Claim 1

A method for analyzing a static analog integrated circuit layout, comprising steps of:
S1: extracting parasitic parameters from a schematic of and a layout of a design circuit to acquire corresponding simulation netlists net_1 and net_2;
S2: identifying the simulation netlists net_1 and net_2 to construct device-node hypergraph or graph structures netgraph_1 and netgraph_2 reflecting a circuit topological structure;
S3: establishing, based on the device-node hypergraph or graph structures, lists devs_list_1 and devs_list_2 to be analyzed and corresponding to the netgraph_1 and netgraph_2, wherein the lists to be analyzed comprise device groups and circuit structures; and
S4: calculating frequency characteristics of RC networks between ports of all the device groups, matching the device groups in the devs_list_1 and devs_list_2 one by one, and determining whether mismatch exists between the device groups by comparing the frequency characteristics;
wherein in S4, calculating the frequency characteristics of the RC networks comprises steps of:
S401: providing an independent AC unit source current at i-ports of the RC networks;
S402: performing frequency scanning on each of the RC networks; and
S403: storing node voltage values of j-ports in each frequency point, and performing analysis to acquire a frequency-impedance list.

### Claim 2 (depends on 1)

The method for analyzing the static analog integrated circuit layout according to claim 1, wherein in S4, calculating the frequency characteristics of the RC networks further comprises a step of:
S404: calculating impedances of the RC networks between the i-ports and the j-ports at different frequency points according to an equation (1), wherein the equation (1) is shown as follows:
Zm=√{square root over (R2+X2)} (1),
wherein Zm indicates a magnitude of impedance, R indicates a real part of impedance, and X indicates an imaginary part of impedance; and whether device groups are mismatched is determined by comparing the impedances between the i-ports and the j-ports at different frequencies in the corresponding RC networks of the layout and the schematic.

### Claim 3 (depends on 1)

The method for analyzing the static analog integrated circuit layout according to claim 1, wherein in S4, calculating the frequency characteristics of the RC networks further comprises a step of:
S405: calculating phase differences of the RC networks between the i-ports and the j-ports at different frequency points according to an equation (2), wherein the equation (2) is shown as follows:
θ
=
arctan
⁡
(
X
R
)
,
(
2
)
wherein θ indicates a phase of impedance, R indicates a real part of impedance, and X indicates an imaginary part of impedance; and whether device groups are mismatched is determined by comparing the phases between the i-ports and the j-ports at different frequencies in the corresponding RC networks of the layout and the schematic.

### Claim 4 (depends on 1)

The method for analyzing the static analog integrated circuit layout according to claim 1, wherein in S3, establishing the lists to be analyzed comprises steps of:
S301: determining whether devs_list_1 is preset, when devs_list_1 is preset, detecting a target device group in the netgraph_1, and when devs_list_1 is not preset or when the target device group is not detected, automatically searching in the netgraph_1 for a circuit structure to be matched and generating the devs_list_1; and
S302: searching for corresponding device groups in the netgraph_2 based on device group name in the devs_list_1, and forming the devs_list_2.

### Claim 5 (depends on 4)

The method for analyzing the static analog integrated circuit layout according to claim 4, wherein in S301, a rule of searching for the circuit structure comprises:
starting with any port of an active device to traverse surrounding structures based on the circuit structure to be matched, starting recursive breadth-first search when a target device structure is encountered, ending the traversal when a new active device or ground is encountered, recording the encountered active device, and generating the devs_list_1.

### Claim 6 (depends on 4)

The method for analyzing the static analog integrated circuit layout according to claim 4, wherein in the device-node hypergraph or graph structures, each device structure comprises a parameter sequence, a type, and a port node, wherein a number of the port node varies depending on a device type; and for each node structure, a linked list of a device connected to the node structure and a node index are stored.

### Claim 7 (depends on 6)

The method for analyzing the static analog integrated circuit layout according to claim 6, wherein the parameter sequence stores device parameters comprising a width, a length, and an area.

### Claim 8 (depends on 1)

The method for analyzing the static analog integrated circuit layout according to claim 1, further comprising S5: outputting device groups that failed to match.

### Claim 9 (depends on 1)

The method for analyzing the static analog integrated circuit layout according to claim 1, wherein in S402, a frequency scanning range is given or by default 1 Hz-1 GHz.

### Claim 10 (depends on 1)

The method for analyzing the static analog integrated circuit layout according to claim 1, wherein AC scan matching is further used to perform a circuit mismatch analysis, comprising steps of:
assuming a given current value of Ik(s), acquiring all transfer function sets (8) of V and Ik(s) according to equations (5), (6), and (7), wherein
(G+jωC)V=I (5),
wherein G indicates a conductance matrix, C indicates an inductance matrix, j indicates an imaginary unit, ω indicates an angular frequency, V indicates a node voltage vector, and I indicates a node current vector, and the equation (5) is subjected to Laplace transformation to obtain the equation (6):
(G+sC)V(s)=I(s) (6),
wherein s=jω, V(s) indicates a Laplace-transformed node voltage vector, and I(s) indicates a Laplace-transformed node current vector; and then, assuming I(s) as an input and V(s) as an output according to a transfer function definition, a pole-residue equation (7) is acquired:
Z
⁡
(
s
)
=
∑
i
=
1
n
⁢
k
i
s
-
p
i
,
(
7
)
wherein Z(s) indicates a pole-residue form, ki indicates an ith pole-residue value, pi indicates an ith pole value, and n indicates a number of pole; and assuming a given current value of Ik(s), the all transfer function sets (8) of V and Ik(s) are acquired according to the above equation:
[
T
⁡
(
s
)
1
,
k
T
⁡
(
s
)
2
,
k
⋯
T
⁡
(
s
)
D
,
k
]
⁢
v
;
and
(
8
)
according to the equation (8), performing frequency scanning on each transfer function in the transfer function set; when a difference value of the RC network to be matched is within a specified threshold range, considering matching successful; when the difference value of the RC network to be matched is out of the specified threshold range, determining circuit mismatch.