Nonvolatile memory device supporting high-efficiency I/O interface

A method of operating a memory interface circuit comprising:

• receiving, from a memory controller via first signal lines, a first control signal and a second control signal during a first cycle period and a second cycle period from among time periods included in a predetermined number of cycle periods;
• receiving a write enable signal from a memory controller via a second signal line;
• obtaining a command from the first control signal and the second control signal received during remaining cycle periods of the time periods based on a toggle timing of the write enable signal, when the first control signal and the second control signal received during the first and the second cycle periods are in a first state;
• and
• obtaining an address from the first control signal and the second control signal received during the remaining cycle periods based on a toggle timing of the write enable signal when the first control signal and the second control signal received during the first and the second cycle periods are in a second state.

A memory system comprising:

• a memory controller;
• a memory cell array;
• and
• a memory interface circuit configured to,
• receive, from a memory controller via first signal lines, a first control signal and a second control signal during a first cycle period from among time periods included in a predetermined number of cycle periods from the memory controller via first signal lines,
• receive, from the memory controller via the first signal line, a first control signal and a second control signal during a second cycle period from among the time periods,
• receive a write enable signal from the memory controller via a second signal line,
• obtain a command from the first control signal and the second control signal received during remaining cycle periods of the time periods based on a toggle timing of the write enable signal when the first control signal and the second control signal received during the first and the second cycle periods are in a first state, and
• obtain an address from the first control signal and the second control signal received during the remaining cycle periods based on a toggle timing of the write enable signal when the first control signal and the second control signal received during the first and the second cycle periods are in a second state.