# US 12,112,070 B2 · Page buffer enhancements

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- Number: US 12,112,070 B2
- Document ID: US12112070B2
- Status: Granted
- Kind: B2
- Application number: 18/204,858
- Filed: 2023-06-01
- Published: 2023-09-28
- Granted: 2024-10-08
- Earliest claimed: 2021-03-16
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Neil Buxton; Avadhani Shridhar; Steven Wells; Nicole Ross
- Web page: https://patentgrep.com/patent/US12112070B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24)
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.

## Claims

### Claim 1

A memory storage system comprising:
a non-volatile semiconductor memory device comprising a memory array, a first plurality of buffers, and a second plurality of buffers, wherein the first plurality of buffers are configured to hold data prior to being encoded for storage in the memory array and the second plurality of buffers are configured to hold encoded data for storage in the memory array;
a non-volatile memory interface coupled to the non-volatile semiconductor memory device; and
a controller in communication with the first plurality of buffers and the second plurality of buffers, the controller configured to:
effectuate a transfer a plurality of data payloads to the first plurality of buffers via the non-volatile memory interface, the plurality of data payloads corresponding to data prior to being encoded for storage in the memory array;
issue a read command via the non-volatile memory interface to the non-volatile semiconductor memory device for data associated with the plurality of data payloads; and
in response to the read command, effectuate a transfer of the data associated with the data payloads out of the first plurality of buffers via the non-volatile memory interface.

### Claim 2 (depends on 1)

The memory storage system of claim 1, wherein the second plurality of buffers are configured to encode data from the first plurality of buffers for storage in the memory array.

### Claim 3 (depends on 1)

The memory storage system of claim 1, wherein the controller is further configured to:
issue the read command when the controller is in receipt of any one of: a notification of a program status fail (PSF) signal, and notification of a power loss event.

### Claim 4 (depends on 3)

The memory storage system of claim 3, wherein the controller is configured to:
cause the data payload to be re-encoded for a pseudo single layer cell (pSLC) to be written in the memory array.

### Claim 5 (depends on 1)

The memory storage system of claim 1, wherein the memory array comprises memory cells that each store at least one bit per cell.

### Claim 6 (depends on 5)

The memory storage system of claim 5, wherein the memory array comprises single-level memory cells (SLCs), pseudo single-level memory cells (pSLC), multi-level memory cells (MLCs), triple-level memory cells (TLCs), quad-level memory cells (QLCs) or variable-level memory cells (VLCs).

### Claim 7 (depends on 1)

The memory storage system of claim 1, wherein the non-volatile semiconductor memory device is a CMOS under Array (CuA) NAND semiconductor memory.

### Claim 8 (depends on 1)

The memory storage system of claim 1, wherein the controller comprises a system-on-chip (SoC) controller.

### Claim 9 (depends on 1)

The memory storage system of claim 1, wherein the first and second pluralities of buffers are implemented as page buffers in the nonvolatile semiconductor memory device and incorporated together with the memory array in the nonvolatile semiconductor memory device.

### Claim 10

A method performed by a controller of a memory storage system, the memory system comprising a non-volatile semiconductor memory device comprising a memory array, a first plurality of buffers, and a second plurality of buffers, the first plurality of buffers configured to hold data prior to being encoded for storage in the memory array and the second plurality of buffers configured to hold encoded data for storage in the memory array, the memory system further comprising a non-volatile memory interface coupled to the non-volatile semiconductor memory device, the method comprising:
effectuating a transfer a plurality of data payloads to the first plurality of buffers via the non-volatile memory interface, the plurality of data payloads corresponding to data prior to being encoded for storage in the memory array;
issuing a read command to the non-volatile semiconductor memory device via the non-volatile memory interface for data associated with the plurality of data payloads; and
in response to the read command, effectuating a transfer of the data associated with the data payloads out of the first plurality of buffers via the non-volatile memory interface.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second plurality of buffers are configured to encode data from the first plurality of buffers for storage in the memory array.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
issuing the read command when the controller is in receipt of any one of: a notification of a program status fail (PSF) signal, and notification of a power loss event.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
re-encoding the data payload for a pseudo single layer cell (pSLC) to be written in the memory array.

### Claim 14 (depends on 10)

The method of claim 10, wherein the memory array comprises memory cells that each store at least one bit per cell.

### Claim 15 (depends on 14)

The method of claim 14, wherein the memory array comprises single-level memory cells (SLCs), pseudo single-level memory cells (pSLC), multi-level memory cells (MLCs), triple-level memory cells (TLCs), quad-level memory cells (QLCs) or variable-level memory cells (VLCs).

### Claim 16 (depends on 10)

The method of claim 10, wherein the non-volatile semiconductor memory device is a CMOS under Array (CuA) NAND semiconductor memory.

### Claim 17 (depends on 10)

The method of claim 10, wherein the controller comprises a system-on-chip (SoC) controller.

### Claim 18 (depends on 10)

The method of claim 10, wherein the first and second pluralities of buffers are implemented as page buffers in the nonvolatile semiconductor memory device and incorporated together with the memory array in the nonvolatile semiconductor memory device.