# US 12,112,069 B2 · Memory module and computing device containing the memory module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,069 B2 - Document ID: US12112069B2 - Status: Granted - Kind: B2 - Application number: 18/080,720 - Filed: 2022-12-13 - Published: 2023-04-13 - Granted: 2024-10-08 - Earliest claimed: 2019-06-20 - Assignees: AI Plus, Inc. - Applicants: AI Plus, Inc. - Inventors: John Michael Smolka; Carlos Rene Weissenberg - Web page: https://patentgrep.com/patent/US12112069B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0634: {by changing the state or mode of one or more devices} - G06F 3/0653: {Monitoring storage devices or systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 13/1668: {Details of memory controller} - G06F 13/1694: {Configuration of memory controller to different memory types} - G06F 13/4243: {with synchronous protocol} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the processor to communicate with the one or more DRAMs via a memory interface. ## Claims ### Claim 1 A method, comprising: communicating, by a processor in a memory module, with an external Central Processing Unit (CPU) via a communications interface; receiving, by the processor, data from the external CPU; storing, by the processor, the data in one or more dynamic random-access memories (DRAMs); instructing, by the processor, one or more multiplexers in the memory module to restrict external CPU write and read accesses to the one or more DRAMs; performing, by the processor, one or more operations on the data stored in the one or more DRAMs; writing, by the processor, results from the one or more operations into the one or more DRAMs; instructing, by the processor, the one or more multiplexers to allow external CPU write and read accesses to the one or more DRAMs; communicating, by the processor, to the external CPU that the results are located in the one or more DRAMs. ### Claim 2 (depends on 1) The method of claim 1, wherein the communications interface is a double data rate 4 (DDR4) interface. ### Claim 3 (depends on 1) The method of claim 1, wherein the communications interface is a double data rate 5 (DDR5) interface. ### Claim 4 (depends on 1) The method of claim 1, wherein each of the CPU and the processor has a respective master memory interface, wherein the DRAM has a slave memory interface, and wherein each respective master memory interface communicates with the slave memory interface. ### Claim 5 (depends on 1) The method of claim 1, wherein the memory module is in local mode when the processor instructs the one or more multiplexers in the memory module to restrict external CPU write and read accesses to the one or more DRAMs. ### Claim 6 (depends on 1) The method of claim 1, wherein the memory module is in host mode when the processor instructs the one or more multiplexers in the memory module to allow external CPU write and read accesses to the one or more DRAMs. ### Claim 7 (depends on 1) The method of claim 1, wherein the one or more multiplexers include a multiplexer for switching command, control, and address (CCA). ### Claim 8 (depends on 1) The method of claim 1, wherein the one or more multiplexers include a multiplexer for controlling access to the one or more DRAMs. ### Claim 9 (depends on 1) The method of claim 1, wherein the one or more operations perform image recognition on the data, and wherein the results are the results of the image recognition. ### Claim 10 (depends on 1) The method of claim 1, wherein the one or more operations are AI inferencing algorithms or models to perform AI inferencing. ### Claim 11 A memory module, comprising: a communications interface configured to facilitate communications between a processor in the memory module, with an external Central Processing Unit (CPU), the processor receives data from the external CPU via the communications interface; one or more dynamic random-access memories (DRAMs) configured to store the data; one or more multiplexers that are configured to restrict external CPU write and read accesses to the one or more DRAMs under instruction of the processor; the processor is further configured to: perform one or more operations on the data stored in the one or more DRAMs; write results from the one or more operations into the one or more DRAMs; instruct the one or more multiplexers to allow external CPU write and read accesses to the one or more DRAMs; and communicate to the external CPU that the results are located in the one or more DRAMs. ### Claim 12 (depends on 10) The memory module of claim 10, wherein the communications interface is a double data rate 4 (DDR4) interface. ### Claim 13 (depends on 10) The memory module of claim 10, wherein the communications interface is a double data rate 5 (DDR5) interface. ### Claim 14 (depends on 11) The memory module of claim 11, wherein each of the CPU and the processor has a respective master memory interface, wherein the DRAM has a slave memory interface, and wherein each respective master memory interface communicates with the slave memory interface. ### Claim 15 (depends on 11) The memory module of claim 11, wherein the memory module is in local mode when the processor instructs the one or more multiplexers in the memory module to restrict external CPU write and read accesses to the one or more DRAMs. ### Claim 16 (depends on 11) The memory module of claim 11, wherein the memory module is in host mode when the processor instructs the one or more multiplexers in the memory module to allow external CPU write and read accesses to the one or more DRAMs. ### Claim 17 (depends on 11) The memory module of claim 11, wherein the one or more multiplexers include a multiplexer for switching command, control, and address (CCA). ### Claim 18 (depends on 11) The memory module of claim 11, wherein the one or more multiplexers include a multiplexer for controlling access to the one or more DRAMs. ### Claim 19 (depends on 11) The memory module of claim 11, wherein the one or more operations perform image recognition on the data, and wherein the results are the results of the image recognition. ### Claim 20 (depends on 11) The memory module of claim 11, wherein the one or more operations are AI inferencing algorithms or models to perform AI inferencing. ### Claim 21 A computing device, comprising: one or more memory modules, each memory module comprising: a communications interface configured to facilitate communications between a processor in the memory module, with an external Central Processing Unit (CPU), the processor receives data from the external CPU via the communications interface; one or more dynamic random-access memories (DRAMs) configured to store the data; one or more multiplexers that are configured to restrict external CPU write and read accesses to the one or more DRAMs under instruction of the processor; the processor is further configured to: perform one or more operations on the data stored in the one or more DRAMs; write results from the one or more operations into the one or more DRAMs; instruct the one or more multiplexers to allow external CPU write and read accesses to the one or more DRAMs; and communicate to the external CPU that the results are located in the one or more DRAMs. ### Claim 22 (depends on 21) The computing device of claim 21, wherein the one or more operations are AI inferencing algorithms or models to perform AI inferencing.