# US 12,112,067 B2 · Persistent xSPI STT-MRAM with optional erase operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,067 B2 - Document ID: US12112067B2 - Status: Granted - Kind: B2 - Application number: 17/884,040 - Filed: 2022-08-09 - Published: 2023-09-21 - Granted: 2024-10-08 - Earliest claimed: 2022-03-21 - Assignees: Everspin Technologies, Inc. - Applicants: Everspin Technologies, Inc. - Inventors: Syed M. Alam; Iftekhar Rahman; Pedro Sanchez - Web page: https://patentgrep.com/patent/US12112067B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G11C 11/1675: {Writing or programming circuits or methods} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket} - G06F 3/0673: {Single storage device} - G11C 11/1653: {Address circuits or decoders} - G11C 11/1657: {Word-line or row circuits} - G11C 11/1659: {Cell access} - G11C 11/1697: {Power supply circuits} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming. ## Claims ### Claim 1 A method for programming a memory device comprising a plurality of memory arrays and a non-volatile erase bit value register, the method comprising: receiving a command to program one or more of the plurality of memory arrays; and programming the one or more of the plurality of memory arrays based on the command, wherein the method comprises optionally erasing the one or more of the plurality of memory arrays prior to the programming, wherein the optionally erasing the one or more of the plurality of memory arrays comprises: if a performance or an operation time is critical, assigning an erase bit value in the erase bit value register a first state, or if the performance or operation time is not critical, assigning the erase bit value in the erase bit value register a second state; and receiving the erase bit value from the erase bit value register, wherein, when the erase bit value is in the first state, an optional erase command is activated such as to erase the one or more of the plurality of memory arrays, and, when the erase bit value is in the second state, an optional erase command is not activated such as not to erase the one or more of the plurality of memory arrays. ### Claim 2 (depends on 1) The method of claim 1, further comprising: erasing the one or more of the plurality of memory arrays after receiving the command, wherein the programming of the one or more of the plurality of memory arrays further comprises: programming the one or more of the plurality of memory arrays after erasing the one or more of the plurality of memory arrays. ### Claim 3 (depends on 1) The method of claim 1, wherein the programming of the one or more of the plurality of memory arrays further comprises: programming the one or more of the plurality of memory arrays without erasing the one or more of the plurality of memory arrays prior to the programming. ### Claim 4 (depends on 1) The method of claim 1, wherein the memory device comprises an expanded serial peripheral interface (xSPI) magnetoresistive random-access memory (MRAM) device. ### Claim 5 (depends on 1) The method of claim 1, wherein the memory device further comprises: a bias system connected to the plurality of memory arrays, an error correction code datapath corresponding to each of the plurality of memory arrays, and an interface. ### Claim 6 (depends on 5) The method of claim 5, wherein the bias system comprises one or more magnetoresistive device anti-fuse blocks. ### Claim 7 (depends on 6) The method of claim 6, wherein the interface is connected to the one or more magnetoresistive device anti-fuse blocks. ### Claim 8 (depends on 5) The method of claim 5, wherein the bias system is connected to an array supply or a bias supply. ### Claim 9 (depends on 5) The method of claim 5, wherein the interface is connected to an interface supply and one or more inputs or outputs of the memory device. ### Claim 10 (depends on 1) The method of claim 1, further comprising: receiving a write enable command at the memory device prior to programming the one or more of the plurality of memory arrays; and receiving a write disable command at the memory device after programming the one or more of the plurality of memory arrays. ### Claim 11 A memory device, comprising: a plurality of memory arrays and a non-volatile erase bit value register, wherein the memory device includes: a bias system connected to the plurality of memory arrays, wherein the bias system comprises one or more magnetoresistive device anti-fuse blocks; an error correction code datapath corresponding to each of the plurality of memory arrays; and an interface, wherein the interface is connected to the one or more magnetoresistive device anti-fuse blocks, and wherein the memory device is configured to: receive a command to program one or more of the plurality of memory arrays; and program the one or more of the plurality of memory arrays based on the command, wherein the memory device is configured to optionally erase the one or more of the plurality of memory arrays prior to the programming, wherein the optionally erasing the one or more of the plurality of memory arrays comprises: if a performance or an operation time is critical, assigning an erase bit value in the erase bit value register a first state, or if the performance or operation time is not critical, assigning the erase bit value in the erase bit value register a second state; and receiving the erase bit value from the erase bit value register, wherein, when the erase bit value is in the first state, an optional erase command is activated such as to erase the one or more of the plurality of memory arrays, and, when the erase bit value is in the second state, an optional erase command is not activated such as not to erase the one or more of the plurality of memory arrays. ### Claim 12 (depends on 11) The memory device of claim 11, further configured to: erase the one or more of the plurality of memory arrays after receiving the command, wherein the memory device is further configured, when programming the one or more of the plurality of memory arrays, to: program the one or more of the plurality of memory arrays after erasing the one or more of the plurality of memory arrays. ### Claim 13 (depends on 11) The memory device of claim 11, wherein the memory device is further configured, when programming the one or more of the plurality of memory arrays, to: program the one or more of the plurality of memory arrays without erasing the one or more of the plurality of memory arrays prior to the programming. ### Claim 14 (depends on 11) The memory device of claim 11, wherein the interface is connected to an interface supply and one or more inputs or outputs of the memory device. ### Claim 15 (depends on 11) The memory device of claim 11, further configured to: receive a write enable command at the memory device prior to programming the one or more of the plurality of memory arrays; and receive a write disable command at the memory device after programming the one or more of the plurality of memory arrays. ### Claim 16 A method for programming a memory device comprising a plurality of memory arrays, the method comprising: receiving a write enable command at the memory device, wherein the memory device includes: a bias system connected to the plurality of memory arrays, wherein the bias system comprises one or more magnetoresistive device anti-fuse blocks; an error correction code datapath corresponding to each of the plurality of memory arrays; and an interface, wherein the interface is connected to the one or more magnetoresistive device anti-fuse blocks; performing one or more programming operations for one or more of the plurality of memory arrays after receiving the write enable command, wherein the method comprises optionally erasing the one or more of the plurality of memory arrays prior to the performing the one or more programming operations; wherein the erasing the one or more of the plurality of memory arrays comprises: if a performance or an operation time is critical, assigning an erase bit value in an erase bit value register a first state, or if the performance or operation time is not critical, assigning the erase bit value in the erase bit value register a second state; and receiving the erase bit value from the erase bit value register, wherein, when the erase bit value is in the first state, an erase command is activated such as to erase the one or more of the plurality of memory arrays, and, when the erase bit value is in the second state, an optional erase command is not activated such as not to erase the one or more of the plurality of memory arrays; and receiving a write disable command at the memory device after performing the one or more programming operations; and after programming the one or more of the plurality of memory arrays, receiving a write disable command at the memory device.