# US 12,112,066 B2 · Techniques for firmware enhancement in memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,066 B2 - Document ID: US12112066B2 - Status: Granted - Kind: B2 - Application number: 17/812,609 - Filed: 2022-07-14 - Published: 2024-01-18 - Granted: 2024-10-08 - Earliest claimed: 2022-07-14 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Zhengbo Wang; Jia Sun; Ming Ma - Web page: https://patentgrep.com/patent/US12112066B2 ## CPC - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/061: {Improving I/O performance} - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/063: {for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42)} - G06F 3/0656: {Data buffering arrangements} - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods, systems, and devices for techniques for firmware enhancement in memory devices are described. A memory system may include a volatile memory device and a non-volatile memory device, which may store a node address mapping. A host system in communication with the memory system may transmit a command instructing the memory system to transfer at least a portion of the node address mapping from the non-volatile memory device to the volatile memory device. The memory system may transmit a response to the command to the host system indicating a status associated with transferring the portion of the node address mapping. ## Claims ### Claim 1 A memory system, comprising: a non-volatile memory device; a volatile memory device; and one or more controllers coupled with the non-volatile memory device and the volatile memory device and configured to cause the memory system to: store data in the non-volatile memory device, the non-volatile memory device comprising a first area configured to store a node address mapping and a second area; receive, at the memory system, a command to transfer a portion of the node address mapping from the non-volatile memory device to the volatile memory device that is associated with firmware of the memory system, the node address mapping comprising data indicating a range of address mappings associated with identifying data in node blocks of the second area; and transmit, from the memory system, a response to the command indicating a status associated with transferring the portion of the node address mapping from the non-volatile memory device to the volatile memory device. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to: transfer the portion of the node address mapping from the non-volatile memory device to the volatile memory device based at least in part on receiving the command, wherein the status associated with transferring the portion comprises a successful status based at least in part on transferring the portion. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to: process one or more operations associated with one or more commands received prior to the command to transfer the portion, wherein the status associated with transferring the portion comprises a busy status based at least in part on processing the one or more operations over a threshold duration after receiving the command to transfer the portion. ### Claim 4 (depends on 1) The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to: receive a second command to remove a second portion of the node address mapping from the volatile memory device; and remove the second portion from the volatile memory device based at least in part on one or more fields of the second command indicating the second portion. ### Claim 5 (depends on 1) The memory system of claim 1, wherein the command comprises an indication of a type of information associated with the portion of the node address mapping. ### Claim 6 (depends on 1) The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to: fail to transfer the portion of the node address mapping based at least in part on one or more parameters, wherein the status associated with transferring the portion comprises a failed status based at least in part on failing to transfer the portion. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the one or more controllers are further configured to cause the memory system to: transmit the response comprising an indication of the one or more parameters, the one or more parameters associated with an illegal request, a hardware error, a power threshold, or any combination thereof. ### Claim 8 (depends on 6) The memory system of claim 6, wherein the one or more controllers are configured to cause the memory system to: receive a second command to transfer the portion of the node address mapping to the volatile memory device based at least in part on transmitting the response comprising the failed status. ### Claim 9 (depends on 1) The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to: transfer the portion of the node address mapping from the non-volatile memory device to the volatile memory device based at least in part on the command comprising one or more fields indicating the portion of the node address mapping. ### Claim 10 (depends on 9) The memory system of claim 9, wherein the one or more fields indicate a range of addresses associated with the node address mapping or a portion of the range of addresses. ### Claim 11 (depends on 1) The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to: select the portion of the node address mapping based at least in part on a frequency of access operations associated with the portion satisfying one or more thresholds. ### Claim 12 (depends on 11) The memory system of claim 11, wherein the command comprises a field indicating that the firmware associated with the memory system is configured to select the portion, and selecting the portion is based at least in part on the field. ### Claim 13 (depends on 11) The memory system of claim 11, wherein the one or more controllers are further configured to cause the memory system to: perform one or more access operations using the portion of the node address mapping stored in the volatile memory device; and maintain the portion of the node address mapping in the volatile memory device between operations of the one or more access operations. ### Claim 14 A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system, cause the memory system to: store data in a non-volatile memory device of the memory system, the non-volatile memory device comprising a first area configured to store a node address mapping and a second area; receive, at the memory system, a command to transfer a portion of the node address mapping from the non-volatile memory device to a volatile memory device that is associated with firmware of the memory system, the node address mapping comprising data indicating a range of address mappings associated with identifying data in node blocks of the second area; and transmit, from the memory system, a response to the command indicating a status associated with transferring of the portion of the node address mapping from the non-volatile memory device to the volatile memory device. ### Claim 15 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: transfer the portion of the node address mapping from the non-volatile memory device to the volatile memory device based at least in part on receiving the command, wherein the status associated with transferring the portion comprises a successful status based at least in part on transferring the portion. ### Claim 16 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: process one or more operations associated with one or more commands received prior to the command to transfer the portion, wherein the status associated with transferring the portion comprises a busy status based at least in part on processing the one or more operations over a threshold duration after receiving the command to transfer the portion. ### Claim 17 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: receive a second command to remove a second portion of the node address mapping from the volatile memory device; and remove the second portion from the volatile memory device based at least in part on one or more fields of the second command indicating the second portion. ### Claim 18 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the command comprises an indication of a type of information associated with the portion of the node address mapping. ### Claim 19 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: fail to transfer the portion of the node address mapping based at least in part on one or more parameters, wherein the status associated with transferring the portion comprises a failed status based at least in part on failing to transfer the portion. ### Claim 20 (depends on 19) The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: transmit the response comprising an indication of the one or more parameters, the one or more parameters associated with an illegal request, a hardware error, a power threshold, or any combination thereof. ### Claim 21 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: transfer the portion of the node address mapping from the non-volatile memory device to the volatile memory device based at least in part on the command comprising one or more fields indicating the portion of the node address mapping. ### Claim 22 (depends on 21) The non-transitory computer-readable medium of claim 21, wherein the one or more fields indicate a range of addresses associated with the node address mapping or a portion of the range of addresses. ### Claim 23 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: select the portion of the node address mapping based at least in part on a frequency of access operations associated with the portion satisfying one or more thresholds. ### Claim 24 (depends on 23) The non-transitory computer-readable medium of claim 23, wherein the command comprises a field indicating that the firmware associated with the memory system is configured to select the portion, and selecting the portion is based at least in part on the field. ### Claim 25 A method by a memory system, comprising: storing data in a non-volatile memory device of the memory system, the non-volatile memory device comprising a first area configured to store a node address mapping and a second area; receiving, at the memory system, a command to transfer a portion of the node address mapping from the non-volatile memory device to a volatile memory device that is associated with firmware of the memory system, the node address mapping comprising data indicating a range of address mappings associated with identifying data in node blocks of the second area; and transmitting, from the memory system, a response to the command indicating a status associated with transferring the portion of the node address mapping from the non-volatile memory device to the volatile memory device.