# US 12,112,057 B2 · Strategic memory cell reliability management

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- Number: US 12,112,057 B2
- Document ID: US12112057B2
- Status: Granted
- Kind: B2
- Application number: 17/861,233
- Filed: 2022-07-10
- Published: 2023-01-19
- Granted: 2024-10-08
- Earliest claimed: 2021-07-19
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Marco Sforzin; Daniele Balluchi
- Web page: https://patentgrep.com/patent/US12112057B2

## CPC

- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G11C 11/2255: {Bit-line or column circuits}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0673: {Single storage device}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 29/50008: {of impedance}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

## Claims

### Claim 1

A method, comprising:
activating a set of memory cells in a memory device to perform a memory access, the memory device comprising a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device;
receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells, wherein the signaling comprises one or more bits that indicate whether to disable a flip operation on the set of memory cells;
performing the precharge operation on the set of memory cells based at least in part on the signaling; and
reading the set of memory cells subsequent to activating the set of memory cells and prior to pre-charging the set of memory cells.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, in response to the one or more bits indicating to not disable the flip operation, performing the precharge operation by randomly performing the flip operation on the set of memory cells.

### Claim 3 (depends on 1)

The method of claim 1, wherein the memory device is configured to operate according to a Compute Express Link (CXL) protocol.

### Claim 4

A method, comprising:
activating a set of memory cells in a memory device to perform a memory access, the memory device comprising a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device;
receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells, wherein the signaling comprises one or more bits that indicate whether to disable a flip operation on the set of memory cells; and
performing the precharge operation on the set of memory cells based at least in part on the signaling; and
performing an error correction operation, wherein performance of the error correction operation causes the one or more bits to indicate to disable the flip operation.

### Claim 5 (depends on 4)

The method of claim 4, wherein performing the error correction operation comprises writing a number of different data patterns to the set of memory cells.

### Claim 6 (depends on 4)

The method of claim 4, wherein performing the error correction operation comprises reading a number of different data patterns from the set of memory cells.

### Claim 7 (depends on 1)

The method of claim 1, wherein the set of memory cells is a row of memory cells.

### Claim 8 (depends on 1)

The method of claim 1, wherein the received signaling is associated with a non-user command.

### Claim 9

An apparatus, comprising:
a memory controller configured to receive a command associated with a plurality of memory cells in a memory device; and
a processing device coupled to the plurality of memory cells, the processing device to:
activate a set of memory cells in a memory device to perform a memory access, the memory device comprising a plurality of memory cells of a memory array;
perform a read operation on the set of memory cells;
receive a command to perform a precharge operation on the set of memory cells, wherein the command comprises one or more data units that indicate whether to disable a flip operation on the set of memory cells; and
perform the precharge operation on the set of memory cells.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the processing device is to, in response to the one or more bits indicating to not disable the flip operation, determine whether to perform the flip operation based on a randomized selection of the flip operation.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the processing device is to, in response to determining to perform the flip operation, inverting the data values stored in the set of memory cells.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the processing device is to perform the precharge operation on the set of memory cells using the inverted data values.

### Claim 13 (depends on 9)

The apparatus of claim 9, further comprising a ferroelectric field-effect transistor (FeFET) memory device.

### Claim 14 (depends on 9)

The apparatus of claim 9, further comprising a dynamic random-access memory (DRAM), ferroelectric random-access memory (FeRAM), or a resistive random-access memory (ReRAM) device, or any combination thereof.

### Claim 15

A system, comprising:
a host;
a memory device coupled to the host through a sideband channel, the memory device comprising:
a memory array comprising a plurality of memory cells; and
a memory controller coupled to the memory array, the memory controller to:
activate a set of memory cells in a memory device to perform a memory access, the memory device comprising a plurality of memory cells of a memory array;
perform the memory access on the set of memory cells;
receive a command, via the sideband channel from the host, to perform a precharge operation on the set of memory cells, wherein the command comprises one or more bits that indicates whether to disable a flip operation on the set of memory cells;
perform the precharge operation on the set of memory cells; and
in response to the one or more bits indicating to not disable the flip operation, determine whether to perform the flip operation based on a randomized selection of the flip operation.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the processing device is to:
in response to determining to perform the flip operation, invert the data values stored in the set of memory cells; and
perform the precharge operation on the set of memory cells using the inverted data values.

### Claim 17 (depends on 15)

The system of claim 15, wherein the processing device is to:
receive a message from the host to activate the set of memory cells; and
activate the set of memory cells in response to receiving the message.

### Claim 18 (depends on 15)

The system of claim 15, wherein the processing device is to perform the precharge operation independent of receiving instructions to perform the precharge operation from the host.

### Claim 19 (depends on 15)

The system of claim 15, wherein the processing device is to perform the precharge operation without performing the flip operation in response to performing an error correction operation.