# US 12,112,049 B2 · Reducing energy consumption of self-managed DRAM modules

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- Number: US 12,112,049 B2
- Document ID: US12112049B2
- Status: Granted
- Kind: B2
- Application number: 18/051,150
- Filed: 2022-10-31
- Published: 2024-05-02
- Granted: 2024-10-08
- Earliest claimed: 2022-10-31
- Assignees: Scaleflux, Inc.
- Applicants: ScaleFlux, Inc.
- Inventors: Kelly Fitzpatrick; Yang Liu; Tong Zhang
- Web page: https://patentgrep.com/patent/US12112049B2

## CPC

- G06F 3/0625: {Power saving in storage systems}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06F 3/0631: {by allocating resources to storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A self-managed DRAM module configured to reduce energy consumption. A module is described that includes a plurality of DDR channels and a management engine configured to read and write data blocks to DDR channels according to a process that includes: allocating a set of sub-channels for each DDR channel, wherein each sub-channel includes a subset of the set of DRAM chips; wherein a write operation of a data block includes: encoding the data block to generate an ECC codeword; and writing the ECC codeword into the subset of DRAM chips of a specified sub-channel; and wherein a read operation of the data block includes: reading the ECC codeword from the subset of DRAM chips of the specified sub-channel; and decoding the ECC codeword to obtain the data block.

## Claims

### Claim 1

A method of implementing a self-managed dynamic random-access memory (DRAM) module, comprising:
providing a plurality of double data rate (DDR) channels, each DDR channel having n+2 DRAM chips; and
allocating a set of sub-channels for each DDR channel, wherein each sub-channel includes (n+2)/2 DRAM chips;
performing a write operation of a data block of size b*n where b is a number of bytes, including:
encoding the data block to generate a b (n+2)-byte error correction code (ECC) codeword;
writing 2b bytes of the b (n+2)-byte ECC codeword into each of the (n+2)/2 DRAM chips of a specified sub-channel; and
performing a read operation of the data block, including:
reading 2b bytes from each of the (n+2)/2 DRAM chips of the specified sub-channel to obtain the b (n+2)-byte ECC codeword; and
decoding the b (n+2)-byte ECC codeword to obtain the data block.

### Claim 2 (depends on 1)

The method of claim 1, wherein the write operation further includes, after the encoding:
determining whether the data block qualifies for data folding;
in response to the data block not qualifying for data folding, writing b bytes into each of the n+2 DRAM chips of a DDR channel instead of writing 2b bytes into each of the (n+2)/2 DRAM chips of the specified sub-channel.

### Claim 3 (depends on 2)

The method of claim 2, wherein the read operation further includes:
determining whether the data block qualifies for data folding; and
in response to the data block not qualifying for folding, reading b bytes from the n+2 DRAM chips of the DDR channel instead of reading 2b bytes from each of the (n+2)/2 DRAM chips of the specified sub-channel.

### Claim 4 (depends on 3)

The method of claim 3, wherein determining whether the data block qualifies for data folding includes determining if an address of the data block falls within a predetermined memory region.

### Claim 5

A self-managed dynamic random-access memory (DRAM) module, comprising:
a plurality of DDR channels, each DDR channel having a set of DRAM chips; and
a controller chip configured to read and write data blocks to DDR channels according to a process that includes:
allocating a set of sub-channels for each DDR channel, wherein each sub-channel includes a subset of the set of DRAM chips;
wherein a write operation of a data block includes:
encoding the data block to generate an ECC codeword;
determining whether the data block qualifies for data folding;
in response to the data block not qualifying for data folding, writing the ECC codeword into all of the DRAM chips of a DDR channel;
in response to the data block qualifying for data folding, writing the ECC codeword into the subset of DRAM chips of a specified sub-channel; and
wherein a read operation of the data block includes:
reading the ECC codeword from the subset of DRAM chips of the specified sub-channel; and
decoding the ECC codeword to obtain the data block.

### Claim 6 (depends on 5)

The self-managed DRAM module of claim 5, wherein the read operation further includes:
determining whether the data block qualifies for data folding; and
in response to the data block not qualifying for folding, reading the ECC codeword from all of the DRAM chips of the DDR channel instead of reading the ECC codeword from the subset of DRAM chips of the specified sub-channel.

### Claim 7 (depends on 6)

The self-managed DRAM module of claim 6, wherein determining whether the data block qualifies for data folding includes determining if an address of the data block falls within a predetermined memory region.