# US 12,112,046 B2 · Memory system and operation method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,046 B2 - Document ID: US12112046B2 - Status: Granted - Kind: B2 - Application number: 18/313,372 - Filed: 2023-05-08 - Published: 2023-11-02 - Granted: 2024-10-08 - Earliest claimed: 2019-12-17 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Eujoon Byun - Web page: https://patentgrep.com/patent/US12112046B2 ## CPC - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 3/0611: {in relation to response time} - G06F 3/064: {Management of blocks} - G06F 3/0656: {Data buffering arrangements} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)} - G06F 2212/1024: Latency reduction - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory system may include a nonvolatile memory device comprising a first area and a second area having a higher data I/O operation speed than the first area, and a controller suitable for performing a first read operation on hot data having a hot property, among data stored in the first area. The controller may control the nonvolatile memory device to copy the hot data into the second area during the first read operation, and access the hot data copied in the second area, when a second read operation on the hot data is requested after the first read operation. ## Claims ### Claim 1 An operation method of a memory system, comprising: determining an access mode of an area in which data corresponding to a logical address is stored, when a read request with the logical address is received from a host; performing an error correction operation to data from a first area when the data is stored in the first area having a first access mode and a second area having a second access mode; and determining whether an error of the data from the first area is successfully corrected and transmitting the error-corrected data to the host when the error of the data from the first area is successfully corrected, performing an error correction operation to data from the second area when the error of the data from the first area is not successfully corrected; and transmitting the error-corrected data from the second area to the host. ### Claim 2 (depends on 1) The operation method of claim 1, wherein the speed of a read operation and a program operation of the data stored in the first area is higher than the speed of a read operation and a program operation of the data stored in the second area. ### Claim 3 (depends on 1) The operation method of claim 1, wherein a number of state values of data which is storable in a memory cell included in the first area is less than a number of state values of data which is storable in a memory cell included in the second area. ### Claim 4 (depends on 1) The operation method of claim 1, wherein when the first access mode is a Single-Level Cell (SLC) mode, the second access mode comprises any one of a Multi-Level Cell (MLC) mode, a Triple-Level Cell (TLC) mode and a Quadruple-Level Cell (QLC) mode, wherein the first access mode is an MLC mode, the second access mode comprises any one mode of the TLC mode and the QLC mode, or when the first access mode is the TLC mode, the second access mode comprises the QLC mode. ### Claim 5 An operation method of a memory system, comprising: determining an access mode of an area in which data corresponding to a logical address is stored, when a read request with the logical address is received from a host; performing an error correction operation to data from a first area when the data is stored in the first area having a first access mode and a second area having a second access mode; and determining whether an error of the data from the first area is successfully corrected and transmitting the error-corrected data to the host when the error of the data from the first area is successfully corrected, determining a storage area of hot data, before the read request is received; and copying the hot data, stored in the second area, into the first area through a first copy operation when the hot data is stored only in the second area. ### Claim 6 (depends on 5) The operation method of claim 5, further comprising copying the hot data, stored in the first area, into the second area through a second copy operation when the hot data is stored only in the first area. ### Claim 7 (depends on 5) The operation method of claim 5, wherein the first copy operation comprises: reading out the hot data stored in the second area, and storing the read data in a page buffer; and programming the hot data stored in the page buffer to the first area. ### Claim 8 (depends on 6) The operation method of claim 6, wherein the second copy operation comprises: reading out the hot data stored in the first area, and storing the read data in a page buffer; performing an error correction operation on the hot data stored in the page buffer; and programming the hot data, on which the error correction operation has been performed, to the second area. ### Claim 9 (depends on 6) The operation method of claim 6, wherein a background operation performed on the second area comprises a second copy operation of copying valid data stored in the second area into another memory block having the second access mode. ### Claim 10 (depends on 5) The operation method of claim 5, wherein a background operation performed on the first area comprises a first copy operation of copying valid data stored in the first area into another memory block having the first access mode.