# US 12,112,045 B2 · Storage device and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,112,045 B2 - Document ID: US12112045B2 - Status: Granted - Kind: B2 - Application number: 17/807,185 - Filed: 2022-06-16 - Published: 2023-05-04 - Granted: 2024-10-08 - Earliest claimed: 2021-10-28 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Seongwan Hong; Youngmin Lee - Web page: https://patentgrep.com/patent/US12112045B2 ## CPC - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools} - G06F 1/32: Means for saving power - G06F 3/0632: {by initialisation or re-initialisation of storage systems} - G06F 3/0647: {Migration mechanisms} - G06F 3/0656: {Data buffering arrangements} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)} - G06F 11/1441: {Resetting or repowering} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a buffer memory, a first volatile memory, a second volatile memory, a processor and a buffer context backup circuit. The buffer memory temporarily stores read data and write data. The first and second volatile memories are included in different power domains. The processor generates buffer allocation information, stores the buffer allocation information in the first volatile memory, and controls an access to the buffer memory based on the buffer allocation information. The buffer context backup circuit performs a context backup operation to back up the buffer allocation information from the first volatile memory to the second volatile memory when entering a power down mode and performs a context restoring operation to restore the buffer allocation information from the second volatile memory to the first volatile memory when exiting from the power down mode. ## Claims ### Claim 1 A storage device comprising: a nonvolatile memory device; and a storage controller configured to control operations of the nonvolatile memory device, the storage controller comprising: a buffer memory configured to temporarily store read data read from the nonvolatile memory device and write data to be written in the nonvolatile memory device; a first volatile memory and a second volatile memory included in different power domains; a processor configured to generate buffer allocation information on storage regions of the buffer memory and data stored in the storage regions, store the buffer allocation information in the first volatile memory, and control an access to the buffer memory based on the buffer allocation information; and a buffer context backup circuit configured to perform a context backup operation to read the buffer allocation information from the first volatile memory and store backup information in the second volatile memory when the storage device enters a power down mode, and to perform a context restoring operation to read the backup information from the second volatile memory and store the buffer allocation information in the first volatile memory when the storage device exits from the power down mode, wherein the first volatile memory is included in the processor or the first volatile memory is a tightly coupled memory that is directly connected to the processor without passing through a system bus of the storage device, wherein the second volatile memory is directly connected to the buffer context backup circuit without passing through the system bus. ### Claim 2 (depends on 1) The storage device of claim 1, wherein the buffer memory, the first volatile memory and the processor are included in a power off domain such that power supplied to the power off domain is blocked during the power down mode, and the second volatile memory is included in a power on domain such that power is supplied to the power on domain during the power down mode. ### Claim 3 (depends on 1) The storage device of claim 1, wherein the buffer context backup circuit is configured to generate the backup information by compressing the buffer allocation information when the storage device enters the power down mode, and restore the buffer allocation information by decompressing the backup information when the storage device exits from the power down mode. ### Claim 4 (depends on 1) The storage device of claim 1, wherein the buffer context backup circuit is configured to generate encoded information by error correction code (ECC) encoding of the buffer allocation information and generate the backup information by compressing the encoded information when the storage device enters the power down mode, and generate decompressed information by decompressing the backup information and restore the buffer allocation information by performing ECC decoding of the decompressed information when the storage device exits from the power down mode. ### Claim 5 (depends on 1) The storage device of claim 1, wherein: the first volatile memory is a dynamic random-access memory (DRAM), the second volatile memory is a static random-access memory (SRAM), and a storage capacity of the second volatile memory is smaller than a storage capacity of the first volatile memory. ### Claim 6 (depends on 1) The storage device of claim 1, wherein the storage controller is configured to communicate with a host device according to a universal flash storage (UFS) standard, and the power down mode is a hibernation mode according to the UFS standard. ### Claim 7 (depends on 1) The storage device of claim 1, wherein the storage controller further comprises a power management unit configured to manage power in the storage device, and the buffer context backup circuit is configured to determine timings of starting the context backup operation and the context restoring operation based on an internal mode signal that is provided from the power management unit. ### Claim 8 (depends on 7) The storage device of claim 7, wherein the power management unit is configured to block power from being supplied to the buffer memory, the first volatile memory, the processor and the buffer context backup circuit during the power down mode, and supply power to the second volatile memory during the power down mode. ### Claim 9 (depends on 1) The storage device of claim 1, wherein the storage controller is connected to the nonvolatile memory device through a plurality of channels and the storage controller is configured to generate status information per channel based on respective workloads of the plurality of channels and store the status information in the first volatile memory. ### Claim 10 (depends on 9) The storage device of claim 9, wherein the buffer context backup circuit is configured to read the status information from the first volatile memory and store the status information as a portion of the backup information in the second volatile memory during the context backup operation, and store the states information in the first volatile memory based on the backup information during the context restoring operation. ### Claim 11 (depends on 1) The storage device of claim 1, wherein the first volatile memory is included in a power off domain such that power supplied to the power off domain is blocked during a power down mode, wherein the second volatile memory is included in a power on domain such that power is supplied to the power on domain during the power down mode, wherein the buffer context backup circuit is further configured to compress the buffer allocation information before storing the backup information in the second volatile memory when the storage device enters the power down mode, and to decompress the backup information before storing the buffer allocation information in the first volatile memory when the storage device exits from the power down mode. ### Claim 12 (depends on 11) The storage device of claim 11, wherein the storage controller is configured to communicate with a host device according to a universal flash storage (UFS) standard, and the power down mode is a hibernation mode according to the UFS standard. ### Claim 13 A storage device comprising: a nonvolatile memory device; and a storage controller configured to control operations of the nonvolatile memory device, the storage controller comprising: a buffer memory configured to temporarily store read data read from the nonvolatile memory device and write data to be written in the nonvolatile memory device; a first volatile memory and a second volatile memory included in different power domains; a processor configured to generate buffer allocation information on storage regions of the buffer memory and data stored in the storage regions, store the buffer allocation information in the first volatile memory, and control an access to the buffer memory based on the buffer allocation information; and a buffer context backup circuit configured to perform a context backup operation to read the buffer allocation information from the first volatile memory and store backup information in the second volatile memory when the storage device enters a power down mode, and to perform a context restoring operation to read the backup information from the second volatile memory and store the buffer allocation information in the first volatile memory when the storage device exits from the power down mode, wherein the storage controller is configured to perform a data backup operation to read data from the buffer memory and store backup data in the nonvolatile memory device when the storage device enters the power down mode. ### Claim 14 (depends on 13) The storage device of claim 13, wherein the buffer context backup circuit is configured to perform the context backup operation while the storage controller performs the data backup operation. ### Claim 15 (depends on 13) The storage device of claim 13, wherein the storage controller is configured to store the backup data in a single level cell (SLC) region of the nonvolatile memory device such that each memory cell in the SLC region stores one bit. ### Claim 16 (depends on 13) The storage device of claim 13, wherein the storage controller is configured to perform a data restoring operation to read the backup data and store the backup data in the buffer memory when the storage device exits from the power down mode. ### Claim 17 (depends on 16) The storage device of claim 16, wherein the storage controller is configured to, after the context restoring operation is completed, perform the data restoring operation based on the buffer allocation information that is restored to the first volatile memory by the buffer context backup circuit. ### Claim 18 A method of operating a storage device, comprising: generating buffer allocation information on storage regions of a buffer memory and data stored in the storage regions; storing the buffer allocation information in a first volatile memory; controlling an access to the buffer memory based on the buffer allocation information; performing a context backup operation to read the buffer allocation information from the first volatile memory and store backup information in a second volatile memory when the storage device enter a power down mode; performing a context restoring operation to read the backup information from the second volatile memory and store the buffer allocation information in the first volatile memory when the storage device exits from the power down mode; and performing a data backup operation to read data from the buffer memory and store backup data in a nonvolatile memory when the storage device enters the power down mode. ### Claim 19 (depends on 13) The storage device of claim 13, wherein the first volatile memory is included in the processor or the first volatile memory is a tightly coupled memory that is directly connected to the processor without passing through a system bus of the storage device. ### Claim 20 (depends on 19) The storage device of claim 19, wherein the second volatile memory is directly connected to the buffer context backup circuit without passing through the system bus.