# US 12,111,989 B2 · Method for adjusting resonance frequency of resonance circuit included in electronic pen, electronic pen, and method for manufacturing electronic pen

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- Number: US 12,111,989 B2
- Document ID: US12111989B2
- Status: Granted
- Kind: B2
- Application number: 18/365,892
- Filed: 2023-08-04
- Published: 2023-11-23
- Granted: 2024-10-08
- Earliest claimed: 2019-12-13
- Assignees: Wacom Co., Ltd.
- Applicants: Wacom Co., Ltd.
- Inventors: Shigeru Yamashita; Masamitsu Ito; Toshihiko Horie
- Web page: https://patentgrep.com/patent/US12111989B2

## CPC

- G06F 3/0383: {Signal control means within the pointing device}
- G06F 3/03545: {Pens or stylus}
- H03H 11/02: Multiple-port networks
- G06F 2203/0384: Wireless input, i.e. hardware and software details of wireless interface arrangements for pointing devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

A method is provided for adjusting the resonance frequency of a resonance circuit included in an electronic pen. The method uses adjusting means for adjusting the capacitance of an internal capacitor array and measuring means for measuring an alternating magnetic field generated by the resonance circuit. The method includes (1) a step of changing the state of a predetermined portion of multiple capacitive elements constituting the internal capacitor array, and (2) a step of changing, according to reference resonance frequency variations of the resonance circuit before and after the state change, the state of a portion or all of at least one capacitive element constituting the inner capacitor array other than said predetermined portion of the capacitive elements.

## Claims

### Claim 1

An integrated circuit for an electronic pen, comprising:
an internal capacitor array including a plurality of capacitive elements connected in parallel,
wherein the internal capacitor array includes a mixture of a portion of the capacitive elements of which a state has been changed by a predetermined process and the remaining capacitive elements of which the state remains unchanged,
wherein the remaining capacitive elements and a coil form a resonance circuit, and
circuitry, which is coupled to the internal capacitor array and which is configured to control the electronic pen to transmit a signal using the resonance circuit.

### Claim 2 (depends on 1)

The integrated circuit according to claim 1, comprising a pin for receiving input of a voltage, a current, a signal, and a command from external adjusting means for adjusting a capacitance of the internal capacitor array.

### Claim 3 (depends on 1)

The integrated circuit according to claim 1, wherein each of the plurality of capacitive elements has a different capacitive variation resulting from the predetermined process, and
each of the plurality of capacitive elements is a unit according to which the state change performed by the predetermined process is controlled.

### Claim 4 (depends on 3)

The integrated circuit according to claim 3, wherein the portion of the plurality of the capacitive elements includes a capacitive element in which a capacitance variation resulting from the predetermined process is not minimal.

### Claim 5 (depends on 1)

The integrated circuit according to claim 1, wherein each of the plurality of capacitive elements includes a capacitor having a floating gate formed on a substrate, and
the predetermined process changes a capacitance value of the capacitor by injecting electrical charges into the floating gate of the capacitor included in the capacitive element to be processed.

### Claim 6 (depends on 1)

The integrated circuit according to claim 1, wherein each of the plurality of capacitive elements includes a capacitor having a charge trap insulating film formed on a substrate, and
the predetermined process changes a capacitance value of the capacitor by injecting electrical charges into the charge trap insulating film of the capacitor included in the capacitive element to be processed.

### Claim 7 (depends on 1)

The integrated circuit according to claim 1, wherein each of the plurality of capacitive elements includes a capacitor and a fuse element connected in series, and
the predetermined process cuts the fuse element included in the capacitive element to be processed.

### Claim 8 (depends on 1)

The integrated circuit according to claim 1, wherein each of the plurality of capacitive elements includes a capacitor and an anti-fuse element connected in series, and
the predetermined process causes conduction of the anti-fuse element included in the capacitive element to be processed.

### Claim 9 (depends on 1)

The integrated circuit according to claim 1, wherein each of the plurality of capacitive elements includes a capacitor and a Micro Electro Mechanical Systems switch connected in series, and
the predetermined process switches an on/off-state of the Micro Electro Mechanical Systems switch included in the capacitive element to be processed.