# US 12,111,786 B2 · Active inductor based high-bandwidth 2-state 4-way data serialization apparatus and method

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- Number: US 12,111,786 B2
- Document ID: US12111786B2
- Status: Granted
- Kind: B2
- Application number: 17/338,512
- Filed: 2021-06-03
- Published: 2022-05-12
- Granted: 2024-10-08
- Earliest claimed: 2020-11-09
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Jihwan Kim; Ajay Balankutty; Sandipan Kundu; Stephen Kim; Frank O'Mahony; Kai Yu; Bong Chan Kim
- Web page: https://patentgrep.com/patent/US12111786B2

## CPC

- G06F 13/4291: {using a clocked protocol}
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- H03K 17/6872: {using complementary field-effect transistors}
- H03K 17/6874: {in a symmetrical configuration}
- H03L 7/00: Automatic control of frequency or phase; Synchronisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.

## Claims

### Claim 1

An apparatus comprising:
a pulse generator;
a first transistor coupled to the pulse generator, wherein an output of the pulse generator controls a gate terminal of the first transistor; and
a second transistor coupled is series with the first transistor via a node, wherein a gate terminal of the second transistor is controllable by a resistive device;
a third transistor having a gate terminal coupled to the node; and
a fourth transistor coupled is series with the third transistor, wherein the fourth transistor is controllable by a bias.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the pulse generator receives a data input, a first clock and a second clock, wherein the first clock is phase shifted relative to the second clock by substantially 90 degrees.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein a voltage on a ground node of the pulse generator is tunable via a circuitry.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the circuitry comprises:
a controller to compare a voltage on the ground node with a reference voltage to generate a digital code;
a plurality of switches controllable by the digital code; and
a capacitor coupled to the ground node.

### Claim 5 (depends on 1)

The apparatus of claim 1 comprises a shunt inductor coupled to the third transistor, wherein the shunt inductor is coupled to a supply rail via a resistor.

### Claim 6 (depends on 1)

The apparatus of claim 1 comprises a distributed network of inductors and ESD, wherein one end of the distributed network is coupled to the third transistor while another end of the distributed network is coupled to a package.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the resistive device comprises a transistor coupled to the gate of the second transistor, wherein the resistive device receives a bias voltage.

### Claim 8

An apparatus comprising:
a quadrature clock generator;
four pulse generators, wherein each pulse generator is to receive a pair of clocks from the quadrature clock generator and a data input;
four first transistors, wherein each of the four first transistors is coupled to a pulse generator from among the four pulse generators, and
a second transistor coupled is series with each of the four first transistors via a node, wherein a gate terminal of the second transistor is controllable by a resistive device.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein a voltage on a ground node of the four pulse generators is tunable via a circuitry.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the circuitry comprises:
a controller to compare a voltage on the ground node with a reference voltage to generate a digital code;
a plurality of switches controllable by the digital code; and
a capacitor coupled to the ground node.

### Claim 11 (depends on 8)

The apparatus of claim 8 comprises:
a third transistor having a gate terminal coupled to the node; and
a fourth transistor coupled in series with the third transistor, wherein the fourth transistor is controllable by a bias.

### Claim 12 (depends on 11)

The apparatus of claim 11 comprises a shunt inductor coupled to the third transistor, wherein the shunt inductor is coupled to a supply rail via a resistor.

### Claim 13 (depends on 12)

The apparatus of claim 12 comprises a distributed network of inductors and ESD, wherein one end of the distributed network is coupled to the third transistor while another end of the distributed network is coupled to a package.

### Claim 14 (depends on 8)

The apparatus of claim 8, wherein the resistive device comprises a transistor coupled to the gate terminal of the second transistor, wherein the resistive device receives a bias voltage.

### Claim 15

A system comprising:
a memory;
a processor circuitry coupled to the memory, wherein the processor circuitry is to execute one or more instructions; and
a wireless interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes a serial-deserializer digital-to-analog converter, which comprises:
a pulse generator;
a first transistor coupled to the pulse generator, wherein an output of the pulse generator controls a gate terminal of the first transistor; and
a second transistor coupled is series with the first transistor via a node, wherein a gate terminal of the second transistor is controllable by a resistive device.

### Claim 16 (depends on 15)

The system of claim 15, wherein the pulse generator receives a data input, a first clock and a second clock, wherein the first clock is phase shifted relative to the second clock by substantially 90 degrees.

### Claim 17 (depends on 16)

The system of claim 16, wherein a voltage on a ground node of the pulse generator is tunable via a circuitry.

### Claim 18 (depends on 15)

The system of claim 15, wherein the resistive device comprises a transistor coupled to the gate terminal of the second transistor, wherein the resistive device receives a bias voltage.

### Claim 19 (depends on 18)

The system of claim 18, wherein the transistor comprises a p-type transistor.