# US 12,111,781 B2 · Data burst suspend mode using multi-level signaling

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,111,781 B2
- Document ID: US12111781B2
- Status: Granted
- Kind: B2
- Application number: 18/119,576
- Filed: 2023-03-09
- Published: 2023-09-14
- Granted: 2024-10-08
- Earliest claimed: 2022-03-11
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Eric N. Lee; Leonid Minz; Yoav Weinberg; Ali Feiz Zarrin Ghalam; Luigi Pilolli
- Web page: https://patentgrep.com/patent/US12111781B2

## CPC

- G06F 13/30: with priority control
- G06F 13/1668: {Details of memory controller}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 13/4243: {with synchronous protocol}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

## Claims

### Claim 1

A memory device comprising:
a memory array; and
processing logic, operatively coupled with the memory array, to perform operations comprising:
causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus;
causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode; and
causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the control pin is a chip enable pin.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the second level has a voltage magnitude between the first level and the third level.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the first level is a higher voltage level than the second level, and wherein the second level is a higher voltage level than the third level.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the first level is a lower voltage level than the second level, and wherein the second level is a lower voltage level than the third level.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein:
the data burst is initiated in response to receiving a command accessing the memory device;
the data burst is suspended in response to receiving a priority request; and
the data burst is resumed in response to receiving an indication to resume the data burst corresponding to a completion of the priority request.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the operations further comprise causing the data burst to exit by toggling the logical level of the pin from the second level to the first level.

### Claim 8 (depends on 1)

The memory device claim 1, wherein the operations further comprise:
receiving a command to terminate the data burst; and
in response to receiving the command to be terminated, causing the data burst to be terminated.

### Claim 9

A method comprising:
causing, by a processing device, a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus;
causing, by the processing device, the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode; and
causing, by the processing device, the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

### Claim 10 (depends on 9)

The method of claim 9, wherein the control pin is a chip enable pin.

### Claim 11 (depends on 9)

The method of claim 9, wherein the second level has a voltage magnitude between the first level and the third level.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first level is a higher voltage level than the second level, and wherein the second level is a higher voltage level than the third level.

### Claim 13 (depends on 9)

The method of claim 9, wherein:
the data burst is initiated in response to receiving a command accessing the memory device;
the data burst is suspended in response to receiving a priority request; and
the data burst is resumed in response to receiving an indication to resume the data burst corresponding to a completion of the priority request.

### Claim 14 (depends on 9)

The method of claim 9, further comprising causing, by the processing device, the data burst to exit by toggling the logical level of the pin from the second level to the first level.

### Claim 15 (depends on 9)

The method of claim 9, further comprising:
receiving, by the processing device, a command to terminate the data burst; and
in response to receiving the command to be terminated, causing, by the processing device, the data burst to be terminated.

### Claim 16

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
causing, during a data burst suspend mode, a data burst to be resumed by toggling a logical level of a control pin from a first level corresponding to the data burst suspend mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus; and
causing the data burst to exit by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst inactive mode.

### Claim 17 (depends on 16)

The non-transitory computer-readable storage medium of claim 16, wherein the control pin is a chip enable pin.

### Claim 18 (depends on 16)

The non-transitory computer-readable storage medium of claim 16, wherein the second level has a voltage magnitude between the first level and the third level.

### Claim 19 (depends on 18)

The non-transitory computer-readable storage medium of claim 18, wherein the first level is a higher voltage level than the second level, and wherein the second level is a higher voltage level than the third level.

### Claim 20 (depends on 16)

The non-transitory computer-readable storage medium of claim 16, wherein the operations further comprise, prior to causing the data burst to be resumed, causing the data burst to be suspended by toggling the logical of the control pin from the second level to the first level.