# US 12,111,777 B2 · Multiple pin configurations of memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,111,777 B2 - Document ID: US12111777B2 - Status: Granted - Kind: B2 - Application number: 17/553,525 - Filed: 2021-12-16 - Published: 2022-04-07 - Granted: 2024-10-08 - Earliest claimed: 2020-03-25 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Junichi Sato - Web page: https://patentgrep.com/patent/US12111777B2 ## CPC - G06F 13/1668: {Details of memory controller} - G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus configured to allow data values to be written into the plurality of memory cells of the memory device at a first speed upon connecting to a first host via a first configuration of the plurality of connectors; and allow data values to be written into the plurality of memory cells at a second speed faster than the first speed, upon connecting to a second host via a second configuration of the plurality of connectors. ## Claims ### Claim 1 A device, comprising: memory cells; a communication interface; an integrated circuit package configured to enclose the memory cells and the communication interface; and a plurality of connectors coupled to the communication interface to provide connections from the communication interface to outside of the integrated circuit package; wherein the communication interface is adaptable to use the plurality of connectors in a first configuration to access the memory cells from the outside of the integrated circuit package at a first speed and to use the plurality of connectors in a second configuration to access the memory cells from the outside of the integrated circuit package at a second speed different from the first speed; wherein the plurality of connectors includes a first subset and a second subset different from the first subset; wherein when in the first configuration, the communication interface is configured to provide access to the memory cells using an entire set of the plurality of connectors at the first speed; and wherein when in the first configuration, the communication interface is configured to use the first subset in data transmission at the first speed; and when in the second configuration, the communication interface is configured to use the second subset in data transmission at the second speed. ### Claim 2 (depends on 1) The device of claim 1, wherein the first subset has a first count of connectors; the second subset has second count of connectors; the first count and the second count are different; and the first configuration and the second configuration are configured to operate at a same frequency. ### Claim 3 A device, comprising: memory cells; a communication interface; an integrated circuit package configured to enclose the memory cells and the communication interface; and a plurality of connectors coupled to the communication interface to provide connections from the communication interface to outside of the integrated circuit package; wherein the communication interface is adaptable to use the plurality of connectors in a first configuration to access the memory cells from the outside of the integrated circuit package at a first speed and to use the plurality of connectors in a second configuration to access the memory cells from the outside of the integrated circuit package at a second speed different from the first speed; wherein the plurality of connectors includes a first subset and a second subset different from the first subset; wherein when in the first configuration, the communication interface is configured to provide access to the memory cells using an entire set of the plurality of connectors at the first speed; and wherein when in the first configuration, a first connector in the plurality of connectors is configured to transmit a first type of communications; and when in the second configuration, the first connector in the plurality of connectors is configured to transmit a second type of communications different from the first type. ### Claim 4 (depends on 3) The device of claim 3, wherein the first type and the second type of communication are different ones of a plurality of types, including data transmission, command transmission, address transmission, or control signal transmission, or any combination thereof. ### Claim 5 A method, comprising: determining, by a communication interface of a device having memory cells and the communication interface enclosed within an integrated circuit package, a current configuration of a plurality of connectors of the device being connected to outside of the integrated circuit package; and communicating data, through the communication interface with the outside of the integrated circuit package, at a first speed when the current configuration is a first configuration, or at a second speed, different from the first speed, when the current configuration is a second configuration; wherein the plurality of connectors includes a first subset and a second subset different from the first subset, when the current configuration is the first configuration, the data is communicated via the first subset at the first speed; wherein when the current configuration is the second configuration, the data is communicated via the second subset at the second speed; and wherein the first subset has a first count of connectors; the second subset has second count of connectors; the first count and the second count are different; and the first configuration and the second configuration are configured to operate at a same frequency. ### Claim 6 A method, comprising: determining, by a communication interface of a device having memory cells and the communication interface enclosed within an integrated circuit package, a current configuration of a plurality of connectors of the device being connected to outside of the integrated circuit package; and communicating data, through the communication interface with the outside of the integrated circuit package, at a first speed when the current configuration is a first configuration, or at a second speed, different from the first speed, when the current configuration is a second configuration; wherein the plurality of connectors includes a first subset and a second subset different from the first subset, when the current configuration is the first configuration, the data is communicated via the first subset at the first speed; and wherein when in the first configuration, a first connector in the plurality of connectors is configured to transmit a first type of communications; and when in the second configuration, the first connector in the plurality of connectors is configured to transmit a second type of communications different from the first type. ### Claim 7 (depends on 6) The method of claim 6, wherein the first type and the second type of communication are different ones of a plurality of types, including data transmission, command transmission, address transmission, or control signal transmission, or any combination thereof.