Device, system and method for selectively dropping software prefetch instructions

A method at a processor, the method comprising:

• with a translation lookaside buffer (TLB) manager:
• detecting a first prefetch instruction which corresponds to an instruction identifier, wherein a first entry of a translation lookaside buffer (TLB) comprises translation information which corresponds to the first prefetch instruction;
• based on the detecting, providing first utilization information which indicates that first data, which is prefetched by an execution of the first prefetch instruction, is classified as insufficiently utilized;
• with a registry manager:
• detecting an eviction of the first entry from the TLB while the first utilization information indicates that the first data is classified as insufficiently utilized;
• based on the eviction, generating a second entry of a registry of prefetch instructions, wherein the second entry corresponds to the instruction identifier, the second entry comprising a counter value which represents a number of any subsequent prefetch instructions that are to be dropped and are each to correspond to the instruction identifier;
• and
• with a prefetch controller, dropping a second prefetch instruction based on the second entry.

A system comprising:

• a processor comprising:
• a translation lookaside buffer (TLB) manager comprising circuitry to:
• detect a first prefetch instruction which corresponds to an instruction identifier, wherein a first entry of a TLB is to comprise translation information which corresponds to the first prefetch instruction;
• and
• provide, based on the first prefetch instruction, first utilization information which indicates that first data, which is prefetched by an execution of the first prefetch instruction, is classified as insufficiently utilized;
• a registry manager, coupled to the TLB manager, comprising circuitry to:
• detect an eviction of the first entry from the TLB while the first utilization information indicates that the first data is classified as insufficiently utilized;
• and
• generate, based on the eviction, a second entry of a registry of prefetch instructions, wherein the second entry is to correspond to the instruction identifier, the second entry to comprise a counter value to represent a number of any subsequent prefetch instructions that are to be dropped and are each to correspond to the instruction identifier;
• and
• third circuitry, coupled to the registry, to drop a second prefetch instruction based on the second entry;
• and
• a display device coupled to the processor, the display device to display an image based on a signal communicated with the processor.