# US 12,111,770 B2 · Silent cache line eviction

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- Number: US 12,111,770 B2
- Document ID: US12111770B2
- Status: Granted
- Kind: B2
- Application number: 17/823,408
- Filed: 2022-08-30
- Published: 2024-02-29
- Granted: 2024-10-08
- Earliest claimed: 2022-08-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Tony M. Brewer; Dean E. Walker
- Web page: https://patentgrep.com/patent/US12111770B2

## CPC

- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 9/3816: {Instruction alignment, e.g. cache line crossing}
- G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

System and techniques for silent cache line eviction are described herein. A memory device receives a memory operation from a host. The memory operation establishes data and metadata in a cache line of the memory device upon receipt. The metadata is stored in a memory element that corresponds to the cache line. Later, an eviction trigger to evict the cache line is identified. Then, in response to the eviction trigger, current metadata of the cache line is compared with the metadata in the memory element to determine whether the metadata has changed. the cache line can be evicted without writing to backing memory in response to the metadata being unchanged.

## Claims

### Claim 1

An apparatus comprising:
an interface configured to receive a memory operation from an external entity;
a cache including a cache line; and
processing circuitry configured to:
receive a memory operation via the interface, the memory operation establishing data and metadata in the cache line, wherein the metadata is cache coherency metadata;
store the metadata in a memory element that corresponds to the cache line;
identify an eviction trigger to evict the cache line;
compare, in response to the eviction trigger, current metadata of the cache line with the metadata in the memory element to determine whether the metadata has changed; and
evict the cache line without writing the metadata to backing memory in response to the metadata being unchanged.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the metadata is connection metadata of an interface between a host and the apparatus.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the interface conforms to a Compute Express Link (CXL) interlink standard.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the metadata is CXL meta-state.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein a dirty flag is maintained for the data in the cache line, and wherein the dirty flag is set in response to a change in data in the cache line.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein, to compare the current metadata of the cache line with the metadata in the memory element, the processing circuitry is configured to determine a state of the dirty flag, and wherein the cache line is evicted without writing the metadata to the backing memory is performed in response to both the dirty flag being unset and to the metadata being unchanged.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the processing circuitry is configured to receive multiple updates to the metadata in the cache line between receipt of the memory operation and the eviction trigger.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the processing circuitry is configured to:
receive a second memory operation of a host via the interface, the second memory operation establishing second data and second metadata in a second cache line of the apparatus;
store the second metadata in a second memory element that corresponds to the second cache line;
identify a second eviction trigger to evict the second cache line;
compare, in response to the second eviction trigger, second current metadata of the second cache line and the second memory element to determine whether the second metadata has changed; and
write the second data and the second metadata to the backing memory in response to the second metadata being changed.

### Claim 9

A method comprising:
receiving, at a memory device, a memory operation from a host, the memory operation establishing data and metadata in a cache line of the memory device, wherein the metadata is cache coherency metadata;
storing the metadata in a memory element that corresponds to the cache line;
identifying an eviction trigger to evict the cache line;
comparing, in response to the eviction trigger, current metadata of the cache line with the metadata in the memory element to determine whether the metadata has changed; and
evicting the cache line without writing the metadata to backing memory in response to the metadata being unchanged.

### Claim 10 (depends on 9)

The method of claim 9, wherein the metadata is connection metadata of an interface between the host and the memory device.

### Claim 11 (depends on 10)

The method of claim 10, wherein the interface conforms to a Compute Express Link (CXL) interlink standard.

### Claim 12 (depends on 11)

The method of claim 11, wherein the metadata is CXL meta-state.

### Claim 13 (depends on 9)

The method of claim 9, wherein a dirty flag is maintained for the data in the cache line, and wherein the dirty flag is set in response to a change in data in the cache line.

### Claim 14 (depends on 13)

The method of claim 13, wherein comparing the current metadata of the cache line with the metadata in the memory element includes determining a state of the dirty flag, and wherein evicting the cache line without writing the metadata to the backing memory is performed in response to both the dirty flag being unset and to the metadata being unchanged.

### Claim 15 (depends on 9)

The method of claim 9, comprising receiving multiple updates to the metadata in the cache line between receipt of the memory operation and the eviction trigger.

### Claim 16 (depends on 9)

The method of claim 9, comprising:
receiving a second memory operation of the host, the second memory operation establishing second data and second metadata in a second cache line of the memory device;
storing the second metadata in a second memory element that corresponds to the second cache line;
identifying a second eviction trigger to evict the second cache line;
comparing, in response to the second eviction trigger, second current metadata of the second cache line and the second memory element to determine whether the second metadata has changed; and
writing the second data and the second metadata to the backing memory in response to the second metadata being changed.

### Claim 17

A non-transitory machine readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
receiving, at a memory device, a memory operation from a host, the memory operation establishing data and metadata in a cache line of the memory device, wherein the metadata is cache coherency metadata;
storing the metadata in a memory element that corresponds to the cache line;
identifying an eviction trigger to evict the cache line;
comparing, in response to the eviction trigger, current metadata of the cache line with the metadata in the memory element to determine whether the metadata has changed; and
evicting the cache line without writing the metadata to backing memory in response to the metadata being unchanged.

### Claim 18 (depends on 17)

The non-transitory machine readable medium of claim 17, wherein the metadata is connection metadata of an interface between the host and the memory device.

### Claim 19 (depends on 18)

The non-transitory machine readable medium of claim 18, wherein the interface conforms to a Compute Express Link (CXL) interlink standard.

### Claim 20 (depends on 19)

The non-transitory machine readable medium of claim 19, wherein the metadata is CXL meta-state.

### Claim 21 (depends on 17)

The non-transitory machine readable medium of claim 17, wherein a dirty flag is maintained for the data in the cache line, and wherein the dirty flag is set in response to a change in data in the cache line.

### Claim 22 (depends on 21)

The non-transitory machine readable medium of claim 21, wherein comparing the current metadata of the cache line with the metadata in the memory element includes determining a state of the dirty flag, and wherein evicting the cache line without writing the metadata to the backing memory is performed in response to both the dirty flag being unset and to the metadata being unchanged.

### Claim 23 (depends on 17)

The non-transitory machine readable medium of claim 17, wherein the operations comprise receiving multiple updates to the metadata in the cache line between receipt of the memory operation and the eviction trigger.

### Claim 24 (depends on 17)

The non-transitory machine readable medium of claim 17, wherein the operations comprise:
receiving a second memory operation of the host, the second memory operation establishing second data and second metadata in a second cache line of the memory device;
storing the second metadata in a second memory element that corresponds to the second cache line;
identifying a second eviction trigger to evict the second cache line;
comparing, in response to the second eviction trigger, second current metadata of the second cache line and the second memory element to determine whether the second metadata has changed; and
writing the second data and the second metadata to the backing memory in response to the second metadata being changed.