# US 12,111,765 B2 · Prefetch circuit for cache memory

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- Number: US 12,111,765 B2
- Document ID: US12111765B2
- Status: Granted
- Kind: B2
- Application number: 17/661,394
- Filed: 2022-04-29
- Published: 2023-11-02
- Granted: 2024-10-08
- Earliest claimed: 2022-04-29
- Assignees: Cadence Design Systems, Inc.
- Applicants: Cadence Design Systems, Inc.
- Inventors: Avishai Tvila
- Web page: https://patentgrep.com/patent/US12111765B2

## CPC

- G06F 12/0862: with prefetch
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 2212/1024: Latency reduction
- G06F 2212/507: using speculative control
- G06F 2212/602: Details relating to cache prefetching
- G06F 2212/6024: History based prefetching
- G06F 2212/654: Look-ahead translation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A prefetch circuit coupled to a cache memory circuit includes a storage circuit that stores multiple virtual-to-physical address map entries. In response to receiving an indication of a miss for an access request to the cache memory circuit, the prefetch circuit generates a prefetch address and compares it to a demand address included in the access request. In response to determining that the demand address and the prefetch address are in different memory pages, the prefetch circuit generates a prefetch request using physical page information retrieved from the storage circuit.

## Claims

### Claim 1

An apparatus, comprising:
a cache memory circuit configured to:
store a plurality of lines associated with a corresponding plurality of addresses; and
receive an access request that includes a demand address corresponding to data included in a particular memory page identified by a particular physical page number; and
a prefetch circuit including a storage circuit configured to store a plurality of virtual-to-physical map entries, wherein the prefetch circuit is configured to:
generate a prefetch address using the demand address and a page offset;
in response to receiving an indication from the cache memory circuit that a particular line associated with the demand address is not stored in the cache memory circuit, generate a prefetch request using a different physical page number in response to a determination that the prefetch address is not included in the particular memory page; and
wherein the prefetch circuit is further configured to:
perform a training operation using a plurality of virtual addresses corresponding to physical addresses included in a plurality of accesses to the cache memory circuit;
in response to a determination that a number of times a memory page boundary was crossed during the training operation exceeds a threshold value, activate a cross page mode that tracks a number of page boundary crossings during the training operation; and
update the page offset using a result of the training operation.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the prefetch circuit is further configured, in response to receiving the indication, to generate the prefetch request using the page offset and the particular physical page number in response to a determination that the prefetch address is included in the particular memory page.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a translation lookaside buffer circuit configured to store a plurality of entries including a given entry that maps a given virtual page number to a given physical page number, and wherein the prefetch circuit is further configured, in response to the determination that the prefetch address and the demand address are both included in the particular memory page and in response to a determination that a cross page mode is active, to send a request to the translation lookaside buffer for a particular entry of the plurality of entries that includes the a next physical page number in response to a determination that the next physical page number is not stored in the storage circuit.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the prefetch circuit is further configured to increment the particular physical page number to generate the different physical page number.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the prefetch circuit is further configured to decrement the particular physical page number to generate the different physical page number.

### Claim 6

A method, comprising:
generating, by a prefetch circuit, a first prefetch address using a first offset and a first demand address included in an access request to a cache memory circuit, wherein the first demand address is included in a first memory page identified by a first physical page number; and
in response to receiving, by the prefetch circuit, a first indication from the cache memory circuit that first data associated with the first demand address is not stored in the cache memory circuit:
generating a page offset using the demand address and the first offset;
generating a prefetch request using the page offset and a different physical page number in response to determining that the prefetch address is not included in the first memory page;
performing a training operation using a plurality of virtual addresses corresponding to physical addresses included in a plurality of accesses to the cache memory circuit;
in response to determining that a number of times a memory page boundary was crossed during the training operation exceeds a threshold value, activating, by the prefetch circuit, a cross page mode that tracks a number of page boundary crossings during the training operation; and
updating the page offset using a result of the training operation.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
generating, by the prefetch circuit, a second prefetch address using the first offset and a second demand address received from the cache memory circuit, wherein the second demand address is included in a second memory page identified by a second physical page number; and
in response to receiving, by the prefetch circuit, a second indication from the cache memory circuit that second data associated with the second demand address is not stored in the cache memory circuit, generating a second prefetch request using the page offset and the second physical page number in response to determining that the second prefetch address is included in the second memory page.

### Claim 8 (depends on 6)

The method of claim 6, further comprising, in response to determining that the cross page mode is active and that a next physical page number is not stored in the prefetch circuit, sending a request to a translation lookaside buffer for a particular entry of a plurality of entries stored in the translation lookaside buffer, wherein the particular entry includes the next physical page number.

### Claim 9 (depends on 8)

The method of claim 8, further comprising incrementing the second physical page number to generate the next physical page number.

### Claim 10 (depends on 8)

The method of claim 8, further comprising decrementing the second physical page number to generate the next physical page number.

### Claim 11 (depends on 6)

The method of claim 6, wherein generating the prefetch request using the page offset and the different physical page number includes retrieving the different physical page number from a storage circuit included in the prefetch circuit.