# US 12,111,762 B2 · Dynamic inclusive last level cache

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,111,762 B2
- Document ID: US12111762B2
- Status: Granted
- Kind: B2
- Application number: 17/130,676
- Filed: 2020-12-22
- Published: 2022-06-23
- Granted: 2024-10-08
- Earliest claimed: 2020-12-22
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Ayan Mandal; Leon Polishuk; Oz Shitrit; Joseph Nuzman
- Web page: https://patentgrep.com/patent/US12111762B2

## CPC

- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/1044: Space efficiency improvement
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

## Claims

### Claim 1

An integrated circuit, comprising:
a core; and
a cache controller coupled to the core, the cache controller including circuitry to:
increment a counter value when a hit in a next level cache corresponds to an eviction from a core cache;
perform an evaluation to test for a condition wherein:
a current data hit corresponds to another eviction from the core cache, the current data hit comprising data from a working set; and
the counter value is greater than a threshold;
wherein, where the evaluation indicates a presence of the condition, the circuitry is further to:
identify the data from the working set for dynamic inclusion in the next level cache;
send a shared copy of the identified data to a requesting core of one or more processor cores;
maintain a copy of the identified data in the next level cache; and
set a snoop filter to indicate that the requesting core is valid for the current data hit.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the circuitry is further to:
determine dynamic inclusion of data in the next level cache on a per data line basis.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein, if the current data hit does not correspond to the other eviction from the core cache or if the counter value is not greater than the threshold, the circuitry is further to:
send an exclusive copy of the data to the requesting core;
update an entry in the snoop filter to indicate a core identifier of the requesting core; and
deallocate the data in the next level cache.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the circuitry is further to:
silently drop data to be evicted from a core cache if the data to be evicted from the core cache has a shared copy of the data in the next level cache.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the next level cache comprises a non-inclusive last level cache.

### Claim 6

A method of controlling a cache, the method comprising:
incrementing a counter value when a hit in a next level cache corresponds to an eviction from a core cache;
performing an evaluation to test for a condition wherein:
a current data hit corresponds to another eviction from the core cache, the current data hit comprising data from a working set; and
the counter value is greater than a threshold; and
where the evaluation indicates a presence of the condition:
identifying the data from the working set for dynamic inclusion in the next level cache;
sending a shared copy of the identified data to a requesting core of one or more processor cores;
maintaining a copy of the identified data in the next level cache; and
setting a snoop filter to indicate that the requesting core is valid for the current data hit.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
determining dynamic inclusion of data in the next level cache on a per data line basis.

### Claim 8 (depends on 6)

The method of claim 6, wherein, if the current data hit does not correspond to the other eviction from the core cache or if the counter value is not greater than the threshold, the method further comprises:
sending an exclusive copy of the data to the requesting core;
updating an entry in the snoop filter to indicate a core identifier of the requesting core; and
deallocating the data in the next level cache.

### Claim 9 (depends on 6)

The method of claim 6, further comprising:
silently dropping data to be evicted from a core cache if the data to be evicted from the core cache has a shared copy of the data in the next level cache.

### Claim 10

An apparatus, comprising:
one or more processor cores;
a core cache co-located with and communicatively coupled to the one or more processor cores;
a next level cache co-located with and communicatively coupled to the core cache and the one or more processor cores; and
a cache controller co-located with and communicatively coupled to the core cache, the next level cache, and the one or more processor cores, the cache controller including circuitry to:
increment a counter value when a hit in a next level cache corresponds to an eviction from a core cache;
perform an evaluation to test for a condition wherein:
a current data hit corresponds to another eviction from the core cache, the current data hit comprising data from a working set; and
the counter value is greater than a threshold;
wherein, where the evaluation indicates a presence of the condition, the circuitry is further to:
identify the data from the working set for dynamic inclusion in the next level cache,
send a shared copy of the identified data to a requesting core of the one or more processor cores;
maintain a copy of the identified data in the next level cache; and
set a snoop filter to indicate that the requesting core is valid for the current data hit.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the circuitry is further to:
determine dynamic inclusion of data in the next level cache on a per data line basis.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein, if the current data hit does not correspond to an eviction from the core cache or if the counter value is not greater than the threshold, the circuitry is further to:
send an exclusive copy of the data to the requesting core;
update an entry in the snoop filter to indicate a core identifier of the requesting core; and
deallocate the data in the next level cache.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the circuitry is further to:
silently drop data to be evicted from a core cache if the data to be evicted from the core cache has a shared copy of the data in the next level cache.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the next level cache comprises a non-inclusive last level cache.