Memory cache management based on storage capacity for parallel independent threads

A system comprising:

• a memory device;
• and
• a processing device, operatively coupled to the memory device, the processing device to perform operations comprising:
• programming data items to memory pages of a cache that resides in a first portion of a memory device, wherein each of the data items programmed to the memory pages are associated with at least one of a plurality of processing threads of a host system;
• responsive to determining that a threshold number of memory pages, associated with a first processing thread, are programmed in the cache, identifying, in a first block of the cache, at least one first memory page including a first data item associated with the first processing thread and, in a second block of the cache, at least one second memory page including a second data item associated with the first processing thread;
• copying the first data item and the second data item to a second portion of the memory device while retaining, in each of the first block and the second block, other data items of other processing threads, wherein the second portion of the memory device is provisioned as host space that is addressable by the host system;
• and
• designating the first memory page and the at least one second memory page as invalid.

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

• programing data items to memory pages of a cache that resides in a first portion of a memory device, wherein each of the data items programmed to the memory pages are associated with at least one of a plurality of processing threads of a host system;
• responsive to determining that a threshold number of memory pages, associated with a first processing thread, are programmed in the cache, identifying, in a first block of the cache, at least one first memory page including a first data item associated with a first processing thread and, in a second block of the cache, at least one second memory page including a second data item associated with the first processing thread;
• copying the first data item and the second data item to a second portion of the memory device while retaining, in each of the first block and the second block, other data items of other processing threads, wherein the second portion of the memory device is provisioned as host space that is addressable by the host system;
• and
• designating the first memory page and the at least one second memory page as invalid.