# US 12,111,760 B2 · Memory device and non-transitory computer readable recording medium > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,111,760 B2 - Document ID: US12111760B2 - Status: Granted - Kind: B2 - Application number: 18/215,147 - Filed: 2023-06-27 - Published: 2023-10-26 - Granted: 2024-10-08 - Earliest claimed: 2014-12-29 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Shinichi Kanno - Web page: https://patentgrep.com/patent/US12111760B2 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) - G06F 12/0871: Allocation or management of cache space - G06F 2212/1016: Performance improvement - G06F 2212/1036: Life time enhancement - G06F 2212/1044: Space efficiency improvement - G06F 2212/214: Solid state disk - G06F 2212/222: Non-volatile memory - G06F 2212/311: In host system - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7205: Cleaning, compaction, garbage collection, erase control - G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area. ## Claims ### Claim 1 An information processing system, comprising: a host device; and a memory device connected to the host device, the memory device including: a nonvolatile memory; and a controller electrically connected to the nonvolatile memory and configured to: generate first information including a logical address associated with valid data written in a first area of the nonvolatile memory, transmit the first information to the host device, and in response to receiving, from the host device, second information that is received after the first information is transmitted to the host device, the second information specifying a logical address associated with data to be deleted amongst the valid data in the first area, perform garbage collection on the first area such that first data is copied to a second area of the nonvolatile memory but second data is not copied to the second area of the nonvolatile memory, the first data being the valid data written in the first area and not specified in the second information as the data to be deleted, the second data being the valid data written in the first area and specified in the second information as the data to be deleted, the second area being different from the first area. ### Claim 2 (depends on 1) The information processing system of claim 1, wherein the controller is further configured to generate third information indicating whether data written in the nonvolatile memory is valid or invalid, and generate the first information based on the third information. ### Claim 3 (depends on 2) The information processing system of claim 2, wherein the controller is further configured to generate fourth information relating a logical address of write data written in the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory, and generate the third information based on the fourth information. ### Claim 4 (depends on 2) The information processing system of claim 2, wherein the controller is configured to perform, based on the second information and the third information, the garbage collection on the first area. ### Claim 5 (depends on 1) The information processing system of claim 1, wherein the valid data is updated data in a case where update of the data written in the nonvolatile memory is performed. ### Claim 6 (depends on 1) The information processing system of claim 1, wherein the host device includes a processor, and the data to be deleted is data for which a delete command has been issued by the processor executing an application program or an operating system. ### Claim 7 (depends on 1) The information processing system of claim 1, wherein the first area of the nonvolatile memory is a candidate for the garbage collection. ### Claim 8 (depends on 1) The information processing system of claim 1, wherein the first information further includes an identifier of the first area of the nonvolatile memory. ### Claim 9 (depends on 8) The information processing system of claim 8, wherein the second information includes the identifier of the first area of the nonvolatile memory. ### Claim 10 (depends on 1) The information processing system of claim 1, wherein the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation, and the first area is one of the plurality of blocks. ### Claim 11 A controller for controlling a nonvolatile memory, comprising: an interface electrically connectable to the nonvolatile memory; and a first circuit configured to: generate first information including a logical address associated with valid data written in a first area of the nonvolatile memory, transmit the first information to a host device, and in response to receiving, from the host device, second information that is received after the first information is transmitted to the host device, the second information specifying a logical address associated with data to be deleted amongst the valid data in the first area, perform garbage collection on the first area such that first data is copied to a second area of the nonvolatile memory but second data is not copied to the second area of the nonvolatile memory, the first data being the valid data written in the first area and not specified in the second information as the data to be deleted, the second data being the valid data written in the first area and specified in the second information as the data to be deleted, the second area being different from the first area. ### Claim 12 (depends on 11) The controller of claim 11, wherein the first circuit is further configured to generate third information indicating whether data written in the nonvolatile memory is valid or invalid, and generate the first information based on the third information. ### Claim 13 (depends on 12) The controller of claim 12, wherein the first circuit is further configured to generate fourth information relating a logical address of write data written in the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory, and generate the third information based on the fourth information. ### Claim 14 (depends on 12) The controller of claim 12, wherein the first circuit is configured to perform, based on the second information and the third information, the garbage collection on the first area. ### Claim 15 (depends on 11) The controller of claim 11, wherein the valid data is updated data in a case where update of the data written in the nonvolatile memory is performed. ### Claim 16 (depends on 11) The controller of claim 11, wherein the host device includes a processor, and the data to be deleted is data for which a delete command has been issued by the processor executing an application program or an operating system. ### Claim 17 (depends on 11) The controller of claim 11, wherein the first area of the nonvolatile memory is a candidate for the garbage collection. ### Claim 18 (depends on 11) The controller of claim 11, wherein the first information further includes an identifier of the first area of the nonvolatile memory. ### Claim 19 (depends on 18) The controller of claim 18, wherein the second information includes the identifier of the first area of the nonvolatile memory. ### Claim 20 (depends on 11) The controller of claim 11, wherein the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit for a data erase operation, and the first area is one of the plurality of blocks.