# US 12,111,758 B2 · Synchronized request handling at a memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,111,758 B2
- Document ID: US12111758B2
- Status: Granted
- Kind: B2
- Application number: 17/899,197
- Filed: 2022-08-30
- Published: 2024-02-29
- Granted: 2024-10-08
- Earliest claimed: 2022-08-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Tony M. Brewer; Dean E. Walker
- Web page: https://patentgrep.com/patent/US12111758B2

## CPC

- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 12/0857: {by multiple requestors}
- G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing
- G06F 12/0893: Caches characterised by their organisation or structure
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1024: Latency reduction
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

System and techniques for synchronized request handling at a memory device are described herein. A request is received at the memory device. Here, the request indicates a memory address corresponding to a set of cache lines and a single cache line in the set of cache lines. The memory device maintains a deferred list for the set of cache lines and a set of lists with each member of the set of lists corresponding to one cache line in the set of cache lines. The memory device tests the deferred list to determine that the deferred list is not empty and places the request in the deferred list.

## Claims

### Claim 1

An apparatus comprising:
a set of cache lines;
an interface to receive that indicates a memory address corresponding to the set of cache lines, the memory address corresponding to a single cache line in the set of cache lines, the apparatus maintaining a deferred list for the set of cache lines and a set of lists, each member of the set of lists corresponding to one cache line in the set of cache lines; and
processing circuitry configured to:
test the deferred list to determine that the deferred list is not empty; and
place the request in the deferred list.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the processing circuitry is configured to:
receive, via the interface, a second request indicating a second memory address corresponding to the set of cache lines and a second single cache line in the set of cache lines;
test the deferred list to determine that the deferred list is empty; and
test, in response to the determination that the deferred list is empty, a member of the set of lists that corresponds to the second single cache line to determine whether the member of the set of lists is empty.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the processing circuitry is configured to place, in response to the member of the set of lists not being empty, the second request in the member of the set of lists.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the member of the set of lists is empty.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the processing circuitry is configured to test the second single cache line to determine if the second single cache line is busy.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein, to test the second single cache line, the processing circuitry is configured to read a tag state for the second single cache line.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the processing circuitry is configured to place, in response to the second single cache line being busy, the request in the member of the set of lists.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the processing circuitry is configured to execute, in response to the second single cache line not being busy, the request.

### Claim 9

A method comprising:
receiving a request at a memory device, the request indicating a memory address corresponding to a set of cache lines, the memory address corresponding to a single cache line in the set of cache lines, the memory device maintaining a deferred list for the set of cache lines and a set of lists, each member of the set of lists corresponding to one cache line in the set of cache lines;
testing the deferred list to determine that the deferred list is not empty; and
placing the request in the deferred list.

### Claim 10 (depends on 9)

The method of claim 9, comprising:
receiving a second request indicating a second memory address corresponding to the set of cache lines and a second single cache line in the set of cache lines;
testing the deferred list to determine that the deferred list is empty; and
testing, in response to the determination that the deferred list is empty, a member of the set of lists that corresponds to the second single cache line to determine whether the member of the set of lists is empty.

### Claim 11 (depends on 10)

The method of claim 10, comprising placing, in response to the member of the set of lists not being empty, the second request in the member of the set of lists.

### Claim 12 (depends on 10)

The method of claim 10, wherein the member of the set of lists is empty.

### Claim 13 (depends on 12)

The method of claim 12, comprising testing the second single cache line to determine if the second single cache line is busy.

### Claim 14 (depends on 13)

The method of claim 13, wherein testing the second single cache line includes reading a tag state for the second single cache line.

### Claim 15 (depends on 14)

The method of claim 14, comprising placing, in response to the second single cache line being busy, the request in the member of the set of lists.

### Claim 16 (depends on 14)

The method of claim 14, comprising executing, in response to the second single cache line not being busy, the request.

### Claim 17

A non-transitory machine readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
receiving a request at a memory device, the request indicating a memory address corresponding to a set of cache lines, the memory address corresponding to a single cache line in the set of cache lines, the memory device maintaining a deferred list for the set of cache lines and a set of lists, each member of the set of lists corresponding to one cache line in the set of cache lines;
testing the deferred list to determine that the deferred list is not empty; and
placing the request in the deferred list.

### Claim 18 (depends on 17)

The non-transitory machine readable medium of claim 17, wherein the operations comprise:
receiving a second request indicating a second memory address corresponding to the set of cache lines and a second single cache line in the set of cache lines;
testing the deferred list to determine that the deferred list is empty; and
testing, in response to the determination that the deferred list is empty, a member of the set of lists that corresponds to the second single cache line to determine whether the member of the set of lists is empty.

### Claim 19 (depends on 18)

The non-transitory machine readable medium of claim 18, wherein the operations comprise placing, in response to the member of the set of lists not being empty, the second request in the member of the set of lists.

### Claim 20 (depends on 18)

The non-transitory machine readable medium of claim 18, wherein the member of the set of lists is empty.

### Claim 21 (depends on 20)

The non-transitory machine readable medium of claim 20, wherein the operations comprise testing the second single cache line to determine if the second single cache line is busy.

### Claim 22 (depends on 21)

The non-transitory machine readable medium of claim 21, wherein testing the second single cache line includes reading a tag state for the second single cache line.

### Claim 23 (depends on 22)

The non-transitory machine readable medium of claim 22, wherein the operations comprise placing, in response to the second single cache line being busy, the request in the member of the set of lists.

### Claim 24 (depends on 22)

The non-transitory machine readable medium of claim 22, wherein the operations comprise executing, in response to the second single cache line not being busy, the request.