# US 12,111,727 B2 · Apparatuses, systems, and methods for forced error check and scrub readouts

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- Number: US 12,111,727 B2
- Document ID: US12111727B2
- Status: Granted
- Kind: B2
- Application number: 18/167,768
- Filed: 2023-02-10
- Published: 2023-06-15
- Granted: 2024-10-08
- Earliest claimed: 2021-07-14
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Sujeet Ayyapureddi
- Web page: https://patentgrep.com/patent/US12111727B2

## CPC

- G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/4401: {for self repair}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory may perform a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit may count errors which are detected, and set a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).

## Claims

### Claim 1

An apparatus comprising:
an error check and scrub (ECS) register configured to store a value;
an ECS circuit configured to set the value of the ECS register based at least in part on a count value, the count value indicative of a number of times an error is detected in a memory array of a memory; and
an ECS readout circuit configured to set the value of the ECS register to a value that indicates at least a threshold number of errors based at least in part on an external command, wherein the value is set regardless of the count value.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the ECS readout circuit sets the value of the ECS register based at least in part on the external command independent of a status of an ECS cycle.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the ECS readout circuit is enabled by a setting of the memory, comprising a fuse setting, or a mode register setting, or a combination thereof.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the ECS register includes an errors per row count (EpRC) register, wherein the ECS circuit is configured to increment the count value each time the ECS circuit detects an error along a current row, compare the count value to a stored count value, and replace the stored count value responsive to the count value being greater than the stored count value, and wherein the ECS circuit is configured to set the EpRC register based on the count value exceeding a threshold.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the ECS circuit is configured to set the value if the count exceeds a threshold filter at the end of an ECS cycle.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the apparatus stores pre-set values at least a selected one of which is written to the ECS register responsive to the external command.

### Claim 7

A system comprising:
a controller configured to provide a multi-purpose command; and
a memory configured to receive the multi-purpose command, the memory comprising:
an error check and scrub (ECS) readout circuit configured to set a value of an ECS register based at least in part on the multi-purpose command, wherein the value is set regardless of a status of an ECS cycle.

### Claim 8 (depends on 7)

The system of claim 7, wherein the value that is set at the ECS register indicates at least a threshold number of errors, regardless of a number of errors actually present in the memory.

### Claim 9 (depends on 8)

The system of claim 8, wherein the controller is configured to identify the memory as defective based at least in part on the value that is set at the ECS register indicating at least the threshold number of errors.

### Claim 10 (depends on 9)

The system of claim 9, wherein the controller is configured to shift critical information to memory modules of the memory which are not identified as defective.

### Claim 11 (depends on 7)

The system of claim 7, wherein the controller provides a count to write to the ECS register, or an errors per row counter (EpRC) count value to write to an EpRC register, or a combination thereof.

### Claim 12 (depends on 7)

The system of claim 7, wherein ECS readout circuit is enabled by a setting of the memory, comprising a fuse setting, or a mode register setting, or a combination thereof.

### Claim 13 (depends on 7)

The system of claim 7, further comprising:
an ECS circuit configured to set the value of the ECS register based at least in part on a count value, the count value indicative of a number of times an error is detected in a memory array.

### Claim 14 (depends on 13)

The system of claim 13, wherein the ECS circuit is configured to set the value if the count exceeds a threshold filter at the end of the ECS cycle.

### Claim 15 (depends on 7)

The system of claim 7, wherein the memory stores pre-set values a selected one of which is written to the ECS register responsive to the multi-purpose command.

### Claim 16

A method comprising:
providing a multi-purpose command to a memory; and
forcing an update of a register value of an error check and scrub (ECS) register based at least in part on the multi-purpose command, the forcing of the update of the register value occurring regardless of a status of an ECS cycle.

### Claim 17 (depends on 16)

The method of claim 16, wherein the register value is an errors per row count (EpRC) register.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
providing a count to write to the ECS register, or an errors per row counter (EpRC) count value to write to an EpRC register, or a combination thereof.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
generating an address from a sequence of addresses;
performing an ECS operation on a codeword stored in a location of a memory array specified by the address;
changing a count value if the codeword included an error;
determining if the count value is greater than a threshold responsive to the address being a final address in the sequence of addresses; and
setting the ECS register responsive to the count value being greater than the threshold.

### Claim 20 (depends on 16)

The method of claim 16, wherein providing the multi-purpose command is a part of a test operation for testing the controller response to the ECS register.