# US 12,111,726 B2 · Error rates for memory with built in error correction and detection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,111,726 B2 - Document ID: US12111726B2 - Status: Granted - Kind: B2 - Application number: 18/121,062 - Filed: 2023-03-14 - Published: 2023-07-06 - Granted: 2024-10-08 - Earliest claimed: 2021-05-21 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Monish Shah - Web page: https://patentgrep.com/patent/US12111726B2 ## CPC - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers} - G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)} - G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)} - G06F 11/1056: {Updating check bits on partial write, i.e. read/modify/write} - G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data. ## Claims ### Claim 1 A method, comprising: receiving a write request to write data in a plurality of memory chips with built in error detection, wherein a number of memory chips included in the plurality of memory chips is based on a channel width for a data payload and a bit-width for each memory chip of the plurality of memory chips; determining parity bits for the data; storing the data in a subset of the plurality of memory chips, wherein storing the data in the subset of the plurality of memory chips is based on the bit-width for each memory chip; and storing the parity bits in one memory chip of the plurality of memory chips, wherein the one memory chip is different from the subset of the plurality of memory chips. ### Claim 2 (depends on 1) The method of claim 1, wherein determining the parity bits for the data further includes: performing an exclusive OR operation on each bit of the data. ### Claim 3 (depends on 1) The method of claim 1, wherein the plurality of memory chips are arranged in a horizontal orientation and operate in parallel. ### Claim 4 (depends on 1) The method of claim 1, further comprising: receiving a read request for the data; and receiving in response to the read request, the data from the subset of the memory chips, the parity bits from the one memory chip, and an indication from any of the built in error detection of the plurality of memory chips whether an uncorrectable error (UE) occurred in the data. ### Claim 5 (depends on 4) The method of claim 4, further comprising: identifying a memory chip that sent the indication that the UE occurred; and generating recovered data for the memory chip by rebuilding corrupted data for the memory chip using the parity bits. ### Claim 6 (depends on 5) The method of claim 5, wherein generating the recovered data further comprises: performing an exclusive OR operation with the parity bits and the data from the plurality of memory chips that did not send the indication; and adding, based on the exclusive OR operation, a one or a zero for a bit of the recovered data for the memory chip to result in an even parity where an even number of inputs are true. ### Claim 7 (depends on 1) The method of claim 1, further comprising: receiving a read request of the data; receiving, in response to the read request, the data from the subset of the memory chips, the parity bits from the one memory chip, and an indication that no errors occurred when reading the data from the subset of the memory chips; and verifying whether a silent data corruption occurred in the data in any of the plurality of memory chips. ### Claim 8 (depends on 7) The method of claim 7, wherein verifying whether the silent data corruption occurred further comprises: performing an exclusive OR operation of the data from the subset of the memory chips; comparing an output of the exclusive OR operation with the parity bits; sending a result that an uncorrectable error (UE) occurred indicating that the data is corrupted based on a match not occurring between the output of the exclusive OR operation and the parity bits; and sending a result indicating that no errors occurred in the data based on a match occurring between the output of the exclusive OR operation and the parity bits. ### Claim 9 A method, comprising: receiving a write request to write data in one memory chip of a plurality of memory chips with built in error detection, wherein a number of memory chips included in the plurality of memory chips is based on a channel width for a data payload and a bit-width for each memory chip of the plurality of memory chips; determining a parity bit for the one memory chip; storing the data in the one memory chip, wherein storing the data in the subset of the plurality of memory chips is based on the bit-width for each memory chip; and storing the parity bit in the one memory chip. ### Claim 10 (depends on 9) The method of claim 9, wherein determining the parity bit for the one memory chip further comprises: reading an existing parity bit stored in the one memory chip and performing an exclusive OR operation on the data and the existing parity bit; and updating the parity bit for the one memory chip of the plurality of memory chips based on the exclusive OR operation. ### Claim 11 (depends on 9) The method of claim 9, wherein the plurality of memory chips are arranged in a vertical orientation sharing a single data bus. ### Claim 12 (depends on 11) The method of claim 11, wherein for a given access, only a single memory chip of the plurality of memory chips is active and the single memory chip provides the data and stores the data for the given access. ### Claim 13 (depends on 9) The method of claim 9, further comprising: receiving a read request for the data for a selected memory chip of the plurality of memory chips; performing a read operation, in response to the read request, for the selected memory chip; and determining whether an uncorrectable error (UE) occurred when reading the data from the selected memory chip. ### Claim 14 (depends on 13) The method of claim 13, further comprising: reading the data from the remaining memory chips in the plurality of the memory chips and the parity bit in the memory chip in response an indication that the UE occurred; and generating recovered data for the selected memory chip by rebuilding corrupted data for the selected memory chip by performing an exclusive OR operation with existing parity bits and the data from the remaining memory chips and adding, based on the exclusive OR operation, a one or a zero for the parity bit of the recovered data for the memory chip to result in an even parity where an even number of inputs are true. ### Claim 15 (depends on 13) The method of claim 13, further comprising: completing the read request in response to determining that the UE did not occur; and verifying if a silent data corruption occurred in the data in any of the plurality of memory chips in response to determining that the UE did not occur. ### Claim 16 A method, comprising: receiving a read request for data, wherein a subset of a plurality of memory chips with built in error detection stores the data; receiving, in response to the read request, the data from the subset of the plurality of memory chips and parity bits from one memory chip of the plurality of memory chips, wherein the one memory chip is different form the subset of the plurality of memory chips; and generating recovered data using the parity bits in response to receiving an error notification from a memory chip of the plurality of memory chips indicating that an uncorrectable error (UE) occurred with corrupted data, wherein generating the recovered data includes performing an exclusive OR operation with the parity bits and the data from the plurality of memory chips that did not send the error notification and adding a one or a zero for a bit of the recovered data for the memory chip to result in an even parity where an even number of inputs are true in response to the exclusive OR operation. ### Claim 17 (depends on 16) The method of claim 16, wherein generating the recovered data further comprises: rebuilding the corrupted data using the parity bits by performing an exclusive OR operation with the parity bits and the data from the plurality of memory chips that did not send the error notification. ### Claim 18 (depends on 16) The method of claim 16, further comprising: sending the recovered data.