# US 12,111,723 B2 · Memory repair method and apparatus based on error code tracking

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- Number: US 12,111,723 B2
- Document ID: US12111723B2
- Status: Granted
- Kind: B2
- Application number: 18/233,250
- Filed: 2023-08-11
- Published: 2024-04-04
- Granted: 2024-10-08
- Earliest claimed: 2013-05-24
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware; Ely Tsern
- Web page: https://patentgrep.com/patent/US12111723B2

## CPC

- G06F 11/1044: {with specific ECC/EDC distribution}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1666: {where the redundant component is memory or memory area}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/4401: {for self repair}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- G06F 11/20: using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G11C 29/765: {in solid state disks}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

## Claims

### Claim 1

A memory module, comprising:
a substrate;
at least one integrated circuit (IC) memory device disposed on the substrate; and
an IC buffer chip, the IC buffer chip including:
primary interface circuitry to receive write data from a memory controller along primary data paths;
comparison circuitry to compare information associated with the write data to known failure information;
data extraction circuitry, if the comparison circuitry identifies a correlation between the information associated with the write data and the known failure information, to extract a portion of the write data corresponding to the correlation and to store the portion of the write data in substitute storage; and
secondary interface circuitry to transfer the write data for storage in the at least one memory device along secondary data paths.

### Claim 2 (depends on 1)

The memory module according to claim 1, wherein:
the comparison circuitry is to compare addresses associated with the write data to stored address information associated with known failures.

### Claim 3 (depends on 1)

The memory module according to claim 1, wherein:
the secondary interface circuitry of the IC buffer chip receives read data corresponding to the write data from the at least one memory device along the secondary data paths, the read data from the at least one memory device including a known error bit;
wherein the address comparison circuitry is to compare the addresses associated with the read data to the stored address information associated with the known failures;
wherein the IC buffer chip further includes insertion circuitry to insert the data bit previously stored in the substitute storage location as a replacement for the known error bit in the read data to generate corrected read data; and
wherein the primary interface is to transfer the corrected read data to the memory controller.

### Claim 4 (depends on 3)

The memory module according to claim 3, further comprising:
error detection circuitry to determine whether an error exists in the corrected data;
repair circuitry to repair a failure associated with the error; and
storage to store information regarding the repairing for a subsequent read operation.

### Claim 5 (depends on 4)

The memory module according to claim 4, wherein the error detection circuitry further comprises:
an error detection correction (EDC) circuit to detect and/or correct errors via a Chipkill error detection correction code.

### Claim 6 (depends on 4)

The memory module according to claim 4, wherein the error detection circuitry further comprises:
pipeline circuitry to pipeline the error information associated with the read data along an error bus that couples a data path associated with the read data to a second data path associated with second read data.

### Claim 7 (depends on 1)

The memory module according to claim 1, wherein:
the write data is received by the primary interface circuitry of the IC buffer chip as error detection correction (EDC) encoded write data.

### Claim 8 (depends on 1)

The memory module according to claim 1, wherein secondary interface communicates with the at least one memory device via a dynamic random access memory (DRAM) protocol.

### Claim 9 (depends on 1)

The memory module according to claim 1, wherein:
the portion of the write data corresponding to the correlation comprises at least one data bit.

### Claim 10

A memory module, comprising:
a substrate;
at least one integrated circuit (IC) memory device disposed on the substrate; and
buffer circuitry including:
primary interface circuitry to receive write data from a memory controller along primary data paths;
repair circuitry to detect a correlation between information associated with the write data and known failure information, the repair circuitry to extract a portion of the write data corresponding to the correlation and to store the portion of the write data in substitute storage; and
secondary interface circuitry to transfer the write data for storage in the at least one memory device along secondary data paths.

### Claim 11 (depends on 10)

The memory module according to claim 10, wherein:
the write data is received as error detection correction (EDC) encoded write data.

### Claim 12 (depends on 10)

The memory module according to claim 10, wherein:
the secondary interface circuitry receives read data corresponding to the write data from the at least one memory device along the secondary data paths, the read data from the at least one memory device including a known error portion corresponding to the portion of the write data corresponding to the correlation;
wherein the repair circuitry is to insert the portion of the write data in substitute storage as a replacement for the known error portion in the read data to generate corrected read data; and
wherein the primary interface circuitry is to transfer the corrected read data to the memory controller.

### Claim 13 (depends on 12)

The memory module according to claim 12, further comprising:
error detection circuitry to determine whether an error exists in the corrected read data;
wherein the repair circuitry is to repair a failure associated with the error; and
storage to store information regarding the repairing for a subsequent read operation.

### Claim 14 (depends on 13)

The memory module according to claim 13, wherein the error detection circuitry further comprises:
an error detection correction (EDC) circuit to detect and/or correct errors via a Chipkill error detection correction code.

### Claim 15 (depends on 14)

The memory module according to claim 14, wherein the error detection circuitry further comprises:
pipeline circuitry to pipeline the error information associated with the read data along an error bus that couples a data path associated with the read data to a second data path associated with second read data.

### Claim 16 (depends on 10)

The memory module according to claim 10, wherein the secondary interface circuitry communicates with the at least one memory device via a dynamic random access memory (DRAM) protocol.

### Claim 17

A memory module, comprising:
multiple dynamic random access memory (DRAM) devices organized into groups;
multiple integrated circuit (IC) buffer chips to buffer data transfers between the multiple DRAM devices and a memory controller, each of the IC buffer chips including:
a primary interface to receive write data from the memory controller along primary data paths;
repair circuitry to detect a correlation between information associated with the write data and known failure information, the repair circuitry to extract a portion of the write data corresponding to the correlation and to store the portion of the write data in substitute storage; and
secondary interface circuitry coupled to a group of the multiple DRAM devices via secondary data paths to transfer the write data for storage in the group of the multiple DRAM devices.

### Claim 18 (depends on 17)

The memory module according to claim 17, wherein:
each of the multiple IC buffer chips is dedicated to one of the groups of the multiple DRAM devices.

### Claim 19 (depends on 17)

The memory module according to claim 17, wherein:
the write data is received as error detection correction (EDC) encoded write data.

### Claim 20 (depends on 19)

The memory circuit of claim 19, wherein:
the encoded write data is coded with a Chipkill error detection correction code.