# US 12,111,682 B2 · Delay synchronization processing device and signal processing device including same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,111,682 B2 - Document ID: US12111682B2 - Status: Granted - Kind: B2 - Application number: 18/026,014 - Filed: 2020-09-14 - Published: 2023-11-16 - Granted: 2024-10-08 - Earliest claimed: 2020-09-14 - Assignees: LG Electronics Inc. - Applicants: LG Electronics Inc. - Inventors: Jongin Choi - Web page: https://patentgrep.com/patent/US12111682B2 ## CPC - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - H03K 3/84: Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - H04N 5/04: Synchronising (for television systems using pulse code modulation H04N7/56) - H04N 21/43: Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware {(real-time communication protocols in data switching networks H04L65/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract The present disclosure relates to a delay synchronization processing apparatus and a signal processing apparatus provided with same. The delay synchronization processing apparatus according to one embodiment of the present disclosure comprises: a delay device to generate a random number and to delay an input asynchronous N-bit signal based on the generated random number; and a synchronization processor configured to perform synchronization processing on the asynchronous N-bit signal delayed by the delay device. Accordingly, errors during non-synchronous bit signal processing can be detected. ## Claims ### Claim 1 A delay synchronization processing device comprising: a delay device configured to generate a random number and to delay an input asynchronous N-bit signal based on the generated random number; a synchronization processor configured to perform synchronization processing on the asynchronous N-bit signal delayed by the delay device; a second synchronization processor configured to perform synchronization processing on the input asynchronous N-bit signal; and a first switch, which in response to a delay synchronization selection signal, is configured to transmit the input asynchronous N-bit signal to the delay device or the second synchronization processor. ### Claim 2 (depends on 1) The delay synchronization processing device of claim 1, wherein the delay device is configured to delay each bit of the input asynchronous N-bit signal based on the generated random number and to output the delayed signal. ### Claim 3 (depends on 1) The delay synchronization processing device of claim 1, wherein the delay device is configured to set a delay time for the each bit of the input asynchronous N-bit signal based on the generated random number, wherein the set delay time is different for the each bit. ### Claim 4 (depends on 1) The delay synchronization processing device of claim 1, wherein the delay device is configured to set a random number of the each bit of the input asynchronous N-bit signal to a multiple of a clock period. ### Claim 5 (depends on 1) The delay synchronization processing device of claim 1, wherein in response to the input asynchronous N-bit signal being a Gray code signal, the delay device is configured to output a normal bit signal without bit error. ### Claim 6 (depends on 1) The delay synchronization processing device of claim 1, wherein the delay device is configured to receive a random number generation control signal, and to generate the random number based on the random number generation control signal. ### Claim 7 (depends on 6) The delay synchronization processing device of claim 6, wherein based on the random number generation control signal, the delay device is configured to generate the random number at varying intervals or to adjust a range for generating the random number. ### Claim 8 (depends on 6) The delay synchronization processing device of claim 6, wherein based on the random number generation control signal, the delay device is configured to perform or not perform some of an operation of generating the random number. ### Claim 9 (depends on 6) The delay synchronization processing device of claim 6, wherein based on random seed information included in the random number generation control signal, the delay device is configured to generate the random number. ### Claim 10 (depends on 1) The delay synchronization processing device of claim 1, further comprising a second switch connected to an output terminal of the second synchronization processor and an output terminal of the synchronization processor, and configured to selectively output an output of the second synchronization processor or an output of the synchronization processor. ### Claim 11 (depends on 10) The delay synchronization processing device of claim 10, further comprising: a third switch configured to receive a clock signal and to selectively output the clock signal to the synchronization processor or the second synchronization processor; and a fourth switch configured to receive a reset signal and to selectively output the reset signal to the synchronization processor or the second synchronization processor. ### Claim 12 (depends on 1) The delay synchronization processing device of claim 1, wherein the synchronization processor comprises: a first flip-flop; a second flip-flop connected to an output terminal of the first flip-flop; and a fifth switch connected to the output terminal of the first flip-flop and an output terminal of the second flip-flop, and to selectively output an output of the first flip-flop or an output of the second flip-flop. ### Claim 13 (depends on 12) The delay synchronization processing device of claim 12, further comprising a third flip-flop connected to an output terminal of the fifth switch. ### Claim 14 A signal processing device comprising a delay synchronization processing device, wherein the delay synchronization processing device comprises: a delay device configured to generate a random number and to delay an input asynchronous N-bit signal based on the generated random number; and a synchronization processor configured to perform synchronization processing on the asynchronous N-bit signal delayed by the delay device, wherein the delay synchronization processing device further comprises: a second synchronization processor configured to perform synchronization processing on the input asynchronous N-bit signal; and a first switch, which in response to a delay synchronization selection signal, is configured to transmit the input asynchronous N-bit signal to the delay device or the second synchronization processor. ### Claim 15 (depends on 14) The signal processing device of claim 14, comprising: a first circuit configured to operate at a first clock frequency and to transmit the asynchronous N-bit signal; and a second circuit configured to operate at a second clock frequency, which is different from the first clock frequency, and to receive the asynchronous N-bit signal from the first circuit, wherein the delay synchronization processing device is located at a front end of the second circuit. ### Claim 16 (depends on 15) The signal processing device of claim 15, wherein the first circuit comprises: a data transmitter configured to transmit the asynchronous N-bit signal to the second circuit; a request signal generator configured to generate a request signal; and a second delay synchronization processing device configured to perform delay and synchronization processing on the request signal. ### Claim 17 (depends on 15) The signal processing device of claim 15, wherein the second circuit comprises: a data receiver configured to receive the asynchronous N-bit signal from the first circuit; an acknowledge (ACK) signal configured to generate an ACK signal; and a third delay synchronization processing device configured to perform delay and synchronization processing on the ACK signal. ### Claim 18 (depends on 14) The signal processing device of claim 14, wherein the synchronization processor comprises: a first flip-flop; a second flip-flop connected to an output terminal of the first flip-flop; and a fifth switch connected to the output terminal of the first flip-flop and an output terminal of the second flip-flop, and to selectively output an output of the first flip-flop or an output of the second flip-flop.