# US 12,111,676 B2 · Bandgap circuit with low power consumption > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,111,676 B2 - Document ID: US12111676B2 - Status: Granted - Kind: B2 - Application number: 17/947,465 - Filed: 2022-09-19 - Published: 2024-03-28 - Granted: 2024-10-08 - Earliest claimed: 2022-09-19 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Giulio Maria Iadicicco; Angelo Bassi - Web page: https://patentgrep.com/patent/US12111676B2 ## CPC - G05F 3/265: {using bipolar transistors only} - G05F 3/30: Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A bandgap circuit that is area efficient and has a low power consumption. The bandgap circuit includes a voltage generator circuit, and a sample and hold circuit coupled to the voltage generator circuit. The voltage generator circuit includes a pair of transistors each connected in a diode configuration and biased with a respective current source of a plurality of current sources of the voltage generator circuit. During a sample phase, the sample and hold circuit samples a first voltage between a first base and a first emitter of a first transistor of the pair of transistors and a second voltage between a second base and a second emitter of a second transistor of the pair of transistors. During a hold phase subsequent to the sample phase, the sample and hold circuit generates an output voltage as a combination of the sampled first and second voltages. ## Claims ### Claim 1 A bandgap circuit comprising: a voltage generator circuit including a pair of transistors each connected in a diode configuration and biased with a respective current source of a plurality of current sources of the voltage generator circuit; and a sample and hold circuit coupled to the voltage generator circuit, the sample and hold circuit configured to: sample, during a sample phase, a first voltage between a first base and a first emitter of a first transistor of the pair of transistors and a second voltage between a second base and a second emitter of a second transistor of the pair of transistors, and generate, during a hold phase subsequent to the sample phase, an output voltage as a combination of the sampled first and second voltages. ### Claim 2 (depends on 1) The bandgap circuit of claim 1, wherein, during the sample phase, the voltage generator circuit is enabled and generates the first and second voltages. ### Claim 3 (depends on 1) The bandgap circuit of claim 1, wherein the voltage generator circuit is disabled during the hold phase. ### Claim 4 (depends on 1) The bandgap circuit of claim 1, wherein, during the hold phase, the sample and hold circuit is further configured to buffer the sampled first and second voltages. ### Claim 5 (depends on 1) The bandgap circuit of claim 1, wherein the hold phase has a duration longer than a duration of the sample phase. ### Claim 6 (depends on 1) The bandgap circuit of claim 1, wherein a first current source of the plurality of current sources is connected to a first collector of the first transistor and a second current source of the plurality of current sources is connected to a second collector of the second transistor. ### Claim 7 (depends on 6) The bandgap circuit of claim 6, wherein a second current of the second current source is a scaled up version of a first current of the first current source. ### Claim 8 (depends on 1) The bandgap circuit of claim 1, wherein, during the sample phase, the sample and hold circuit is further configured to: sample the first voltage by a first capacitor connected between the first base of the first transistor and a first input of an operational amplifier of the sample and hold circuit; and sample the second voltage by a second capacitor connected between the second base of the second transistor and a second input of the operational amplifier. ### Claim 9 (depends on 8) The bandgap circuit of claim 8, wherein, during the sample phase, the first and second inputs of the operational amplifier are biased to a reference voltage. ### Claim 10 (depends on 9) The bandgap circuit of claim 9, wherein the reference voltage is set to the output voltage generated during the hold phase. ### Claim 11 (depends on 8) The bandgap circuit of claim 8, wherein, during the hold phase, a voltage at the first and second inputs of the operational amplifier decreases. ### Claim 12 (depends on 8) The bandgap circuit of claim 8, wherein: the second capacitor discharges during the hold phase on a plurality of capacitors of the sample and hold circuit; and the output voltage is generated during the hold phase as a scaled version of the second voltage subtracted by a scaled version of the first voltage. ### Claim 13 (depends on 1) The bandgap circuit of claim 1, wherein the first and second transistors are bipolar junction transistors. ### Claim 14 A method of operating a bandgap circuit, the method comprising: sampling, during a sample phase of a sample and hold circuit of the bandgap circuit, a first voltage between a first base and a first emitter of a first transistor of a voltage generator circuit of the bandgap circuit and a second voltage between a second base and a second emitter of a second transistor of the voltage generator circuit, each of the first and second transistors connected in a diode configuration and biased with a respective current source of a plurality of current sources of the voltage generator circuit; and generating, during a hold phase of the sample and hold circuit subsequent to the sample phase, an output voltage as a combination of the sampled first and second voltages. ### Claim 15 (depends on 14) The method of claim 14, further comprising: enabling the voltage generator circuit during the sample phase to generate the first and second voltages; and disabling the voltage generator circuit during the hold phase. ### Claim 16 (depends on 14) The method of claim 14, further comprising: buffering, by the sample and hold circuit, the sampled first and second voltages during the hold phase. ### Claim 17 (depends on 14) The method of claim 14, further comprising: sampling, during the sample phase, the first voltage by a first capacitor of the sample and hold circuit connected between the first base of the first transistor and a first input of an operational amplifier of the sample and hold circuit; and sampling, during the sample phase, the second voltage by a second capacitor of the sample and hold circuit connected between the second base of the second transistor and a second input of the operational amplifier. ### Claim 18 (depends on 17) The method of claim 17, further comprising: connecting, during the sample phase, the first and second inputs of the operational amplifier to a reference voltage; and setting the reference voltage to the output voltage generated during the hold phase. ### Claim 19 (depends on 17) The method of claim 17, further comprising: decreasing, during the hold phase, a voltage at the first and second inputs of the operational amplifier. ### Claim 20 (depends on 17) The method of claim 17, further comprising: discharging the second capacitor during the hold phase on a plurality of capacitors of the sample and hold circuit; and generating the output voltage during the hold phase as a scaled version of the second voltage subtracted by a scaled version of the first voltage.