# US 12,111,582 B2 · Substrate stage and substrate processing system using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,111,582 B2 - Document ID: US12111582B2 - Status: Granted - Kind: B2 - Application number: 18/351,571 - Filed: 2023-07-13 - Published: 2023-11-09 - Granted: 2024-10-08 - Earliest claimed: 2021-03-05 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yu-Huan Chen; Yu-Chih Huang; Ya-An Peng; Shang-Chieh Chien; Li-Jui Chen; Heng-Hsin Liu - Web page: https://patentgrep.com/patent/US12111582B2 ## CPC - G03F 7/70725: {control} - G03F 7/70991: {Connection with other apparatus, e.g. multiple exposure stations, particular arrangement of exposure apparatus and pre-exposure and/or post-exposure apparatus; Shared apparatus, e.g. having shared radiation source, shared mask or workpiece stage, shared base-plate; Utilities, e.g. cable, pipe or wireless arrangements for data, power, fluids or vacuum} - G03F 7/70716: {Stages} - G03F 7/70758: {Drive means, e.g. actuators, motors for long- or short-stroke modules or fine or coarse driving} - G03F 7/70775: {Position control, e.g. interferometers or encoders for determining the stage position} - G03F 7/70866: {of mask or workpiece} - G03F 7/7095: {Materials, e.g. materials for housing, stage or other support having particular properties, e.g. weight, strength, conductivity, thermal expansion coefficient} - G03F 7/70358: {Scanning exposure, i.e. relative movement of patterned beam and workpiece during imaging} - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) ## Abstract A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a base layer, a magnetic shielding layer disposed on the base layer, a carrier layer disposed on the magnetic shielding layer, a receiver disposed on the carrier layer, a storage layer disposed between the base layer and the magnetic shielding layer, and a magnetic shielding element disposed on the carrier layer and surrounding the receiver. ## Claims ### Claim 1 A semiconductor substrate stage for carrying a substrate, comprising: a base layer; a magnetic shielding layer disposed on the base layer; a carrier layer disposed on the magnetic shielding layer; a receiver disposed on the carrier layer; a storage layer disposed between the base layer and the magnetic shielding layer; and a magnetic shielding element disposed on the carrier layer and surrounding the receiver. ### Claim 2 (depends on 1) The semiconductor substrate stage as claimed in claim 1, wherein a width of the metal layer is greater than the receiver. ### Claim 3 (depends on 1) The semiconductor substrate stage as claimed in claim 1, wherein the magnetic shielding element is in contact with a sidewall of the receiver. ### Claim 4 (depends on 1) The semiconductor substrate stage as claimed in claim 1, wherein the magnetic shielding element and the receiver have identical heights. ### Claim 5 (depends on 1) The semiconductor substrate stage as claimed in claim 1, wherein the magnetic shielding element and the receiver are in contact with an identical surface of the carrier layer. ### Claim 6 (depends on 1) The semiconductor substrate stage as claimed in claim 1, wherein the storage layer comprises hydrogen source in contact with the base layer. ### Claim 7 (depends on 6) The semiconductor substrate stage as claimed in claim 6, wherein the hydrogen source does not overlap the magnetic shielding element in a direction perpendicular to the base layer. ### Claim 8 A semiconductor substrate stage for carrying a substrate, comprising: a base layer having a channel; a magnetic shielding layer disposed on the base layer; a carrier layer disposed on the magnetic shielding layer; a receiver disposed on the carrier layer, wherein the receiver is configured to receive a signal that controls the movement of the semiconductor substrate stage; and a storage layer disposed between the base layer and the magnetic shielding layer, comprising a water storage device partially exposed from the channel. ### Claim 9 (depends on 8) The semiconductor substrate stage as claimed in claim 8, wherein the storage layer further comprises an energy storage device disposed adjacent to the water storage device, wherein the energy storage device is not exposed from the channel. ### Claim 10 (depends on 8) The semiconductor substrate stage as claimed in claim 8, wherein the storage layer further comprises a hydrogen source disposed adjacent to the water storage device, wherein the hydrogen source is not exposed from the channel. ### Claim 11 (depends on 8) The semiconductor substrate stage as claimed in claim 8, wherein a width of the water storage device is greater than a width of the channel. ### Claim 12 (depends on 8) The semiconductor substrate stage as claimed in claim 8, wherein the magnetic shielding layer comprises: an insulating layer in contact with the storage layer; and a metal layer in contact with the carrier layer. ### Claim 13 (depends on 12) The semiconductor substrate stage as claimed in claim 12, wherein the insulating layer is in contact with the carrier layer. ### Claim 14 (depends on 13) The semiconductor substrate stage as claimed in claim 13, wherein the insulating layer is in contact with sidewalls of the metal layer. ### Claim 15 A semiconductor substrate stage for carrying a substrate, comprising: a base layer, wherein a channel is formed on the base layer; a magnetic shielding layer disposed on the base layer, comprising an insulating layer and a metal layer, wherein sidewalls of the metal layer are in contact with the insulating layer; a carrier layer disposed on the magnetic shielding layer; a receiver disposed in a recess formed on a top surface of the carrier layer; and a storage layer exposed from the channel. ### Claim 16 (depends on 15) The semiconductor substrate stage as claimed in claim 15, wherein a width of the metal layer is greater than the receiver. ### Claim 17 (depends on 15) The semiconductor substrate stage as claimed in claim 15, wherein the metal layer overlaps the receiver in a vertical direction that is perpendicular to a top surface of the carrier layer. ### Claim 18 (depends on 15) The semiconductor substrate stage as claimed in claim 15, wherein a thickness of the metal layer is less than a thickness of the insulating layer. ### Claim 19 (depends on 15) The semiconductor substrate stage as claimed in claim 15, wherein the insulating layer and the metal layer are in contact with a bottom surface of the carrier layer, and the bottom surface faces the storage layer. ### Claim 20 (depends on 15) The semiconductor substrate stage as claimed in claim 15, further comprising a magnetic shielding element overlaps the metal layer in a vertical direction that is perpendicular to a top surface of the carrier layer.