# US 12,111,356 B2 · System and method for access control of a plurality of instruments embedded in a semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,111,356 B2 - Document ID: US12111356B2 - Status: Granted - Kind: B2 - Application number: 17/766,849 - Filed: 2020-10-09 - Published: 2024-02-22 - Granted: 2024-10-08 - Earliest claimed: 2019-10-11 - Applicants: Erik Larsson - Inventors: Erik Larsson - Web page: https://patentgrep.com/patent/US12111356B2 ## CPC - G01R 31/318555: {Control logic} - G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)} - G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)} - G01R 31/318558: {Addressing or selecting of subparts of the device under test} - G01R 31/318314: {Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages (simulation software G01R31/318357; emulators G06F11/261)} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A system for accessing a plurality of instruments embedded in a semiconductor device includes a hardware interface and a test controller for testing the semiconductor device or generating test patterns for the semiconductor device, wherein the test controller comprises an instrument connectivity language and a procedural description language configuration for operating the instruments. The test controller is configured to perform the steps of: testing at least one functionality of each of the plurality of instruments, thereby receiving a fault status of each of the plurality of instruments; and based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration. ## Claims ### Claim 1 A system for accessing a plurality of instruments embedded in a semiconductor device, the system comprising: a hardware interface, such as a test access port or a functional port, configured to access a control mechanism for controlling the plurality of instruments; a test controller for testing the semiconductor device and generating test patterns for the semiconductor device, wherein the test controller comprises an instrument connectivity language and a procedural description language configuration for operating the instruments, the test controller being configured to perform the steps of: testing at least one functionality of each of the plurality of instruments by accessing the control mechanism for controlling the plurality of instruments through the hardware interface, thereby receiving a fault status of each of the plurality of instruments; and based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration, wherein the instruments are reconfigurable scan networks and the testing is scan testing, wherein the test block comprises a repair component configured to automatically exclude specific faulty scan registers from a scan-path in the scan testing. ### Claim 2 (depends on 1) The system for accessing a plurality of instruments embedded in a semiconductor device according to claim 1, wherein the control mechanism for controlling the plurality of instruments through the hardware interface comprises segment insertion bits for the plurality of instruments. ### Claim 3 (depends on 2) The system for accessing a plurality of instruments embedded in a semiconductor device according to claim 2, wherein the segment insertion bits are configurable to include or exclude the instruments. ### Claim 4 (depends on 1) The system for accessing a plurality of instruments embedded in a semiconductor device according to claim 1, wherein the test block in the semiconductor device is configured to exclude faulty hardware parts for specific instruments based on the fault status. ### Claim 5 (depends on 1) The system for accessing a plurality of instruments embedded in a semiconductor device according to claim 1, wherein the test block in the semiconductor device is configured to replace a faulty hardware part for a specific instrument with a corresponding repair part. ### Claim 6 (depends on 1) The system for accessing a plurality of instruments embedded in a semiconductor device according to claim 1, wherein the step of testing at least one functionality of each of the plurality of instruments comprises generating and shifting a test sequence through scan chains of all instruments. ### Claim 7 (depends on 1) The system for accessing a plurality of instruments embedded in a semiconductor device according to claim 1, wherein the test block is configured to set up an active scan-path such that only instruments without faulty scan chains are included in the testing. ### Claim 8 (depends on 1) The system for accessing a plurality of instruments embedded in a semiconductor device according to claim 1, wherein the test controller is configurable to send a test command to the test block through the hardware interface and/or wherein the test controller is configurable to send a repair command to the test block through the hardware interface. ### Claim 9 (depends on 1) The system for accessing a plurality of instruments embedded in a semiconductor device according to claim 1, wherein the system comprises an implementation of a IEEE Std. 1687 for accessing the instruments. ### Claim 10 (depends on 1) The system for accessing a plurality of instruments embedded in a semiconductor device according to claim 1, wherein the hardware interface is a JTAG interface or a UART interface. ### Claim 11 A method for testing a semiconductor device, the method comprising: configuring a test by defining interconnections of a plurality of instruments in the semiconductor device, wherein the instruments are reconfigurable scan networks, using an instrument connectivity language and defining operations of the instruments using a procedural description language; accessing access a control mechanism for controlling the plurality of instruments through a hardware interface to test at least one functionality of each of a plurality of instruments, thereby receiving a fault status of each of the plurality of instruments; configuring a test block in the semiconductor device to automatically exclude faulty hardware parts for specific instruments by using a repair component based on the fault status of the plurality of instruments, or excluding a procedural description language command specifically related to the faulty hardware parts; and performing a full test using all the plurality of instruments in the semiconductor device without updating the defined interconnections and operations of the instruments in the test. ### Claim 12 A method for accessing a plurality of instruments embedded in a semiconductor device, wherein the instruments are reconfigurable scan networks, the method comprising the steps of: providing a hardware interface, such as a test access port or a functional port, configured to access a control mechanism for controlling the plurality of instruments; providing a test controller for testing the semiconductor device and generating test patterns for the semiconductor device, wherein the test controller comprises an instrument connectivity language and a procedural description language configuration for operating the instruments; testing at least one functionality of each of the plurality of instruments by accessing the control mechanism for controlling the plurality of instruments through the hardware interface, thereby receiving a fault status of each of the plurality of instruments; and based on the fault status of the plurality of instruments, configure a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration by using a repair component to automatically exclude specific faulty scan registers from a scan-path in the scan testing.