# US 12,111,354 B2 · Detection circuit of clock anomaly and method, clock circuit, chip and radar

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,111,354 B2
- Document ID: US12111354B2
- Status: Granted
- Kind: B2
- Application number: 18/131,344
- Filed: 2023-04-05
- Published: 2023-10-12
- Granted: 2024-10-08
- Earliest claimed: 2022-04-08
- Assignees: Suteng Innovation Technology Co., Ltd.
- Applicants: Suteng Innovation Technology Co., Ltd.
- Inventors: Yumin Liao; Junling Zang; Yueqing Yang
- Web page: https://patentgrep.com/patent/US12111354B2

## CPC

- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A detection circuit of clock anomaly and method, a clock circuit, a chip, and a radar are provided. The detection circuit of clock anomaly includes: a first clock frequency determining unit, configured to determine a first clock frequency of a received first clock signal; a reference determining unit, configured to determine a reference corresponding to the first clock signal, where the reference is determined based on a second clock signal or a timestamp; and a clock anomaly detection unit, connected to the first clock frequency determining unit and the reference determining unit separately and configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference. This application can improve reliability of the clock signal, thereby improving personal safety and property safety of a user.

## Claims

### Claim 1

A detection circuit of clock anomaly, comprising:
a first clock frequency determining unit, configured to determine a first clock frequency of a received first clock signal;
a reference determining unit, configured to determine a reference corresponding to the first clock signal, wherein the reference is determined based on at least one of a second clock signal or a timestamp; and
a clock anomaly detection unit, connected to the first clock frequency determining unit and the reference determining unit separately and configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference;
wherein the reference determining unit comprises a first reference time period determining circuit, configured to determine a first reference time period, wherein the first reference time period is a time period during which a number of pulses of the second clock signal reaches a first count value;
wherein the first clock frequency determining unit comprises a first counter, connected to the clock anomaly detection unit and configured to: perform pulse counting on the first clock signal within the first reference time period to obtain a second count value, and transmit the second count value to the clock anomaly detection unit;
wherein the first reference time period determining circuit comprises:
a second counter, connected to the clock anomaly detection unit and configured to: in response to a first enabling signal, perform pulse counting on the second clock signal until reaching a preset first count value, transmit the first count value to the clock anomaly detection unit, and output a counting completion signal; and
a counting control unit, connected to the first counter and the second counter separately and configured to: output the first enabling signal to the first counter and the second counter, output a counting ending instruction to the first counter in response to the counting completion signal, and send a second enabling signal to the clock anomaly detection unit, wherein the counting control unit comprises a delay control circuit.

### Claim 2 (depends on 1)

The detection circuit according to claim 1, wherein the reference determining unit further comprises
a second reference time period determining circuit, configured to determine a second reference time period, wherein the second reference time period is a time period between respective timestamps of two packets.

### Claim 3 (depends on 1)

The detection circuit according to claim 1, wherein
the clock anomaly detection unit comprises a first count comparator, configured to compare a count difference with a first preset difference threshold, compare the count difference with a second preset difference threshold to perform anomaly detection on the first clock signal, or both, wherein the count difference is a difference between the first count value and the second count value, and the first preset difference threshold is different from the second preset difference threshold.

### Claim 4 (depends on 3)

The detection circuit according to claim 3, further comprising:
a first reference time period configuration unit, connected to the first count comparator and configured to store at least one of the first preset difference threshold or the second preset difference threshold, and transmit at least one of the first preset difference threshold or the second preset difference threshold to the first count comparator.

### Claim 5 (depends on 1)

The detection circuit according to claim 1, wherein the first reference time period determining circuit further comprises: a second clock generating unit, connected to the second counter and configured to output the second clock signal to the second counter.

### Claim 6 (depends on 1)

The detection circuit according to claim 1, wherein the second reference time period determining circuit comprises:
a time unpacking unit, connected to a first network and configured to parse a packet received from the first network to obtain the timestamp, wherein the packet transmitted via the first network has the timestamp.

### Claim 7 (depends on 6)

The detection circuit according to claim 6, wherein the clock anomaly detection unit comprises a second count comparator, the second count comparator comprises a buffer unit, configured to receive the timestamp in response to the second count comparator and store the second count value, and the second count value is received from the first counter.

### Claim 8 (depends on 6)

The detection circuit according to claim 6, further comprising:
a second reference time period configuration unit, connected to the clock anomaly detection unit and configured to store a mapping relationship between a timestamp difference and a preset difference threshold, and the clock anomaly detection unit finds the preset difference threshold corresponding to the timestamp difference.

### Claim 9 (depends on 1)

The detection circuit according to claim 1, further comprising:
an anomaly handling unit, comprising at least one of the following:
an interrupt signal generating module, configured to output an interrupt signal when the first clock signal is abnormal; or
a reset signal generating module, configured to output a reset signal when the first clock signal is abnormal.