# US 12,111,352 B2 · Machine learning for syncing multiple FPGA ports in a quantum system

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- Number: US 12,111,352 B2
- Document ID: US12111352B2
- Status: Granted
- Kind: B2
- Application number: 17/582,207
- Filed: 2022-01-24
- Published: 2023-07-27
- Granted: 2024-10-08
- Earliest claimed: 2022-01-24
- Assignees: Quantum Machines
- Applicants: Quantum Machines
- Inventors: Avishai Ziv; Ori Weber; Nissim Ofek
- Web page: https://patentgrep.com/patent/US12111352B2

## CPC

- G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/31712: {Input or output aspects}
- G06N 10/20: Models of quantum computing, e.g. quantum circuits or universal quantum computers
- G06N 10/60: Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms
- G06N 20/00: Machine learning
- G01R 31/3167: Testing of combined analog and digital circuits {(testing ADC's H03M1/1071)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.

## Claims

### Claim 1

A method comprising:
setting a tap, of a plurality of taps, for each of a plurality of multi-tap delay lines;
sending a test signal, via each of a plurality of asynchronous ports, to a destination, wherein each of the plurality of asynchronous ports is operably coupled to a multi-tap delay line of the plurality of multi-tap delay lines;
measuring a phase of the test signal at the destination corresponding to each of the plurality of asynchronous ports;
repeating the phase measurement after setting each tap of the plurality of taps;
selecting one tap, for each of the plurality of asynchronous ports, according to phase measurements for each of the plurality of asynchronous ports; and
generating a tap estimate function according to selected taps for the plurality of asynchronous ports.

### Claim 2 (depends on 1)

The method of claim 1, wherein the tap estimate function is generated according to a setup-and-hold time for each of the plurality of asynchronous ports.

### Claim 3 (depends on 1)

The method of claim 1, wherein a field programmable gate array (FPGA) comprises the plurality of asynchronous ports.

### Claim 4 (depends on 3)

The method of claim 3, wherein the FPGA comprises the plurality of multi-tap delay lines.

### Claim 5 (depends on 3)

The method of claim 3, wherein the tap estimate function is generated according to phase measurements from a plurality of FPGAs.

### Claim 6 (depends on 1)

The method of claim 1, wherein the destination comprises one or more digital-to-analog converters (DACs).

### Claim 7 (depends on 1)

The method of claim 1, wherein the test signal is a sinusoidal wave.

### Claim 8 (depends on 1)

The method of claim 1, wherein the test signal comprises a pulse.

### Claim 9 (depends on 1)

The method of claim 1, wherein the selected tap, for a particular port of the plurality of asynchronous ports, corresponds to a period of constant phase.

### Claim 10 (depends on 1)

The method of claim 1, wherein the selected tap, for a particular port of the plurality of asynchronous ports, is determined according to one or more phase changes.

### Claim 11

A system comprising:
a signal generator operable to generate a test signal;
a plurality of multi-tap delay lines operable to receive the test signal, wherein each multi-tap delay line is operable to output a delayed test signal corresponding to a tap of a plurality of taps;
a plurality of asynchronous ports, wherein each asynchronous port is operable to send delayed test signals to a destination; and
an application for generating a tap estimate function, wherein:
for each of the plurality of asynchronous ports, the application is operable to measure a plurality of phase values, the plurality of phase values corresponding the plurality of taps,
for each of the plurality of asynchronous ports, the application is operable to select the tap from the plurality of phase values, and
the tap estimate function is generated according to selected taps for each of the plurality of asynchronous ports.

### Claim 12 (depends on 11)

The system of claim 11, wherein the tap estimate function is generated according to a setup-and-hold time for each of the plurality of asynchronous ports.

### Claim 13 (depends on 11)

The system of claim 11, wherein a field programmable gate array (FPGA) comprises the plurality of asynchronous ports.

### Claim 14 (depends on 13)

The system of claim 13, wherein the FPGA comprises the plurality of multi-tap delay lines.

### Claim 15 (depends on 13)

The system of claim 13, wherein the tap estimate function is generated according to phase measurements from a plurality of FPGAs.

### Claim 16 (depends on 11)

The system of claim 11, wherein the destination comprises one or more digital-to-analog converters (DACs).

### Claim 17 (depends on 11)

The system of claim 11, wherein the test signal is a sinusoidal wave.

### Claim 18 (depends on 11)

The system of claim 11, wherein the test signal comprises a pulse.

### Claim 19 (depends on 11)

The system of claim 11, wherein the selected tap, for a particular port of the plurality of asynchronous ports, corresponds to a period of constant phase.

### Claim 20 (depends on 11)

The system of claim 11, wherein the selected tap, for a particular port of the plurality of asynchronous ports, is determined according to one or more phase changes.