# US 12,111,348 B2 · Evaluation module and evaluation method for evaluating multichip module lifespan

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- Number: US 12,111,348 B2
- Document ID: US12111348B2
- Status: Granted
- Kind: B2
- Application number: 17/483,411
- Filed: 2021-09-23
- Published: 2022-03-31
- Granted: 2024-10-08
- Earliest claimed: 2020-09-28
- Assignees: Robert Bosch GmbH; Huazhong University of Science and Technology
- Applicants: Robert Bosch GmbH; Huazhong University of Science and Technology
- Inventors: Lin Liang; Lubin Han; Yong Kang; Xudan Liu; Maojun He
- Web page: https://patentgrep.com/patent/US12111348B2

## CPC

- G01R 31/2855: {Environmental, reliability or burn-in testing}
- G01R 31/2874: {related to temperature}
- H10D 62/8325: {Silicon carbide}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 90/00: Package configurations
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07354: {changes in dispositions}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An evaluation module configured to evaluate the lifespan of a multichip module, the multichip module comprising a first substrate and multiple chips under evaluation, includes a second substrate, configured to be the same as the first substrate, and having attachment positions corresponding to the attachment positions on the first substrate, and at least one evaluation chip, configured to be the same as the multiple chips under evaluation. The number of evaluation chips is less than the number of chips under evaluation by at least one. The at least one evaluation chip is arranged at an attachment position on the second substrate, such that the at least one evaluation chip and the chip under evaluation arranged at the corresponding attachment position on the multichip module have the same cooling performance and sustain the same thermal stress. The present disclosure also discloses a method for evaluating the lifespan of a multichip module.

## Claims

### Claim 1

An evaluation module configured to evaluate the lifespan of a multichip module, the multichip module including a first substrate and multiple chips under evaluation arranged at at least one attachment position on the first substrate, comprising:
a second substrate configured to be the same as the first substrate of the multichip module, and having at least one attachment position, each of the at least one attachment position corresponding to a corresponding one of the at least one attachment position on the first substrate of the multichip module; and
at least one evaluation chip configured to be the same as the multiple chips under evaluation of the multichip module, wherein:
the number of the at least one evaluation chip is less than the number of the multiple chips under evaluation of the multichip module by at least one; and
the at least one evaluation chip is arranged at at least one of the at least one attachment position on the second substrate such that the at least one evaluation chip and the chip under evaluation arranged at the corresponding one of the at least one attachment position of the first substrate on the multichip module have the same cooling performance and sustain the same thermal stress during evaluation.

### Claim 2 (depends on 1)

The evaluation module according to claim 1, wherein the at least one evaluation chip is a single chip.

### Claim 3 (depends on 1)

The evaluation module according to claim 1, wherein:
the evaluation module further comprises at least one chip substitute arranged on the second substrate; and
the at least one evaluation chip and the at least one chip substitute are configured to keep the structure of the evaluation module balanced during evaluation.

### Claim 4 (depends on 3)

The evaluation module according to claim 3, wherein the at least one chip substitute is arranged at one of the at least one attachment position on the second substrate.

### Claim 5 (depends on 4)

The evaluation module according to claim 4, wherein:
the at least one evaluation chip and the at least one chip substitute are arranged at vertices of a polygon at least comprising a triangle; and
a center of gravity line of a component arranged above the at least one evaluation chip and the at least one chip substitute passes through a region defined by the polygon when the second substrate is placed horizontally.

### Claim 6 (depends on 3)

The evaluation module according to claim 3, wherein the at least one chip substitute is made of a material matched to thermomechanical properties of the at least one evaluation chip.

### Claim 7 (depends on 6)

The evaluation module according to claim 6, wherein:
the at least one evaluation chip is a silicon carbide MOSFET chip; and
the at least one chip substitute is made of silicon carbide.

### Claim 8 (depends on 1)

The evaluation module according to claim 1, wherein:
the multichip module further comprises a third substrate;
the multiple chips under evaluation of the multichip module are arranged between the first substrate and third substrate of the multichip module;
the evaluation module further comprises a fourth substrate; and
at least one of the at least one evaluation chip of the evaluation module is arranged between the second substrate and fourth substrate of the evaluation module.

### Claim 9 (depends on 8)

The evaluation module according to claim 8, wherein:
the evaluation module further comprises at least one chip substitute arranged between the second substrate and the fourth substrate; and
the at least one evaluation chip and the at least one chip substitute are configured to keep the fourth substrate structurally balanced during evaluation when the second substrate is placed horizontally.

### Claim 10 (depends on 1)

A method for evaluating the lifespan of a multichip module, comprising:
providing the evaluation module according to claim 1;
determining multiple sets of test stresses and the number of the evaluation modules;
performing accelerated lifespan testing of the evaluation module;
calculating a reliability function of the evaluation module under each determined set of the multiple sets of test stresses;
calculating a lifespan prediction model of the evaluation module;
calculating a reliability function of the multichip module under each of the determined multiple sets of test stresses;
calculating a lifespan prediction model of the multichip module; and
calculating the lifespan of the multichip module under actual operating conditions.

### Claim 11 (depends on 10)

The method according to claim 10, wherein:
calculating the reliability function of the evaluation module under each of the determined multiple sets of test stresses uses the following formula:
R
e
⁡
(
t
)
=
e
-
(
t
η
)
β
where Re(t) is the reliability of the evaluation module, t is the lifespan of the evaluation module, η is a scale factor, and β is a shape factor.

### Claim 12 (depends on 11)

The method according to claim 11, wherein:
the lifespan prediction model of the evaluation module is expressed by the following formula:
Nfe=αe·(ΔTje)βe
where Nfe is the lifespan of the evaluation module, ΔTje is the extent of fluctuation of chip junction temperature of the evaluation module, and αe and βe are calculation constants of the evaluation module.

### Claim 13 (depends on 12)

The method according to claim 12, wherein:
the reliability function of the multichip module under each of the determined multiple sets of test stresses is expressed by the following formula:
Rm(t)=R1(t)·R2(t)·R3(t)· . . . ·Rn(t)
where n is the number of chips of the multichip module, Rm(t) is the reliability of the multichip module, and R1(t) to Rn(t) are the respective reliabilities of the chips of the multichip modules.

### Claim 14 (depends on 13)

The method according to claim 13, wherein:
the lifespan prediction model of the multichip module is expressed by the following formula:
Nfm=αm·(ΔTj)βm
where Nfm is the lifespan of the multichip module, ΔTj is the extent of fluctuation of the chip junction temperature of the multichip module, and αm and βm are calculation constants of the multichip module.

### Claim 15 (depends on 14)

The method according to claim 14, wherein:
the lifespan of the multichip module under actual operating conditions is calculated by the following formula:
Nfmr=αm·(ΔTjr)βm
where Nfmr is the lifespan of the multichip module under actual operating conditions, and ΔTjr is the extent of fluctuation of chip junction temperature of the multichip module under actual operating conditions.

### Claim 16 (depends on 13)

The method according to claim 13, wherein calculating the reliability function of the multichip module further comprises:
calculating the lifespan of each chip in the multichip module using calculation constants αe and βe of the evaluation module and the following formula:
Nfi=αe·(ΔTji)βe
where i is an integer from 1 to n, n is the number of chips in the multichip module, Nfi is the lifespan of each chip of the multichip module, and ΔTji is the extent of fluctuation of chip junction temperature of each chip of the multichip module; and
calculating the reliability function of each chip of the multichip module using the following formula:
R
i
⁡
(
t
)
=
e
-
(
t
-
(
N
fi
-
N
fe
)
η
)
β
where i is an integer from 1 to n, n is the number of chips in the multichip module, Ri(t) is the reliability of each chip of the multichip module, and t is the lifespan of the multichip module.

### Claim 17 (depends on 16)

The method according to claim 16, wherein the extent of fluctuation of chip junction temperature of each chip of the multichip module is obtained by simulation.