# US 12,111,346 B2 · Crack detector units and the related semiconductor dies and methods

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- Number: US 12,111,346 B2
- Document ID: US12111346B2
- Status: Granted
- Kind: B2
- Application number: 17/697,925
- Filed: 2022-03-18
- Published: 2023-09-21
- Granted: 2024-10-08
- Earliest claimed: 2022-03-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Huan-Neng Chen; Shao-Yu Li
- Web page: https://patentgrep.com/patent/US12111346B2

## CPC

- G01R 31/2601: {Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence)}
- G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)}
- G01R 31/54: Testing for continuity
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10P 74/20: characterised by the properties tested or measured, e.g. structural or electrical properties
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

## Claims

### Claim 1

A crack detector unit (CDU), comprising:
a switching circuit configured to enable a crack sensor;
the crack sensor configured to be electrically connected to the switching circuit, the ground, and an operating voltage; and
a logic circuit configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit, and an output of the logic circuit indicates whether the crack sensor contains a crack,
wherein the switching circuit comprises a p-type metal-oxide-semiconductor field-effect transistors (PMOS), a source electrode of the PMOS is connected to the operating voltage, a drain electrode of the PMOS is connected to the crack sensor and the logic circuit, and a gate electrode of the PMOS is connected to the logic circuit.

### Claim 2 (depends on 1)

The CDU of claim 1, wherein the crack sensor comprises a metal pattern.

### Claim 3 (depends on 1)

The CDU of claim 1, wherein the crack sensor comprises multiple metal layers and vias.

### Claim 4 (depends on 1)

The CDU of claim 1, wherein the logic circuit comprises an AND logic gate and an NAND logic gate.

### Claim 5 (depends on 4)

The CDU of claim 4, wherein the input of the logic circuit includes a first external input and a second external input, the AND logic gate generates a first output to the switching circuit based on the first external input and the output of the logic circuit, the NAND logic gate generates a second output to the output of the logic circuit based on the second external input and a status of the crack sensor.

### Claim 6 (depends on 1)

The CDU of claim 1, wherein the output of the logic circuit is “1” when no crack is detected.

### Claim 7 (depends on 1)

The CDU of claim 1, wherein the output of the logic circuit is “0” when a crack is detected.

### Claim 8 (depends on 1)

The CDU of claim 1, wherein the CDU is built in a semiconductor die.

### Claim 9 (depends on 1)

The CDU of claim 1, wherein an output of the switching circuit is input to both the crack sensor and the logic circuit.

### Claim 10

A semiconductor die, comprising:
a first crack detector unit (CDU), comprising:
a switching circuit configured to determine whether to enable the first CDU;
a logic circuit electrically connected to the switching circuit; and
a first pattern electrically connected to the switching circuit of the first CDU, the ground, and an operating voltage,
wherein the first CDU determines whether a crack is in the semiconductor die, and
wherein the semiconductor die is connected to a second semiconductor die, the second semiconductor die includes a second pattern, the first CDU determine whether a crack is in the first pattern, the second pattern, or a connection between the semiconductor die and the second semiconductor die.

### Claim 11 (depends on 10)

The semiconductor die of claim 10, wherein the first pattern disposed adjacent to at least one edge of the semiconductor die.

### Claim 12 (depends on 10)

The semiconductor die of claim 10, wherein the semiconductor die comprises an active die or a passive die.

### Claim 13 (depends on 10)

The semiconductor die of claim 10, wherein the second pattern is disposed adjacent to at least one edge of the second semiconductor die.

### Claim 14 (depends on 10)

The semiconductor die of claim 10, wherein the connection between the semiconductor die and the second semiconductor die is through a wafer, a substrate, a print circuit board, or a combination thereof.

### Claim 15 (depends on 11)

The semiconductor die of claim 11, further comprising a second CDU, the second CDU connecting to a third pattern, the third pattern disposed on another edge of the semiconductor die.

### Claim 16 (depends on 15)

The semiconductor die of claim 15, wherein a lookup table based on outputs of the first crack detector and the second crack detector indicates a location of the crack.

### Claim 17 (depends on 10)

The semiconductor die of claim 10, wherein the switching circuit includes a metal-oxide-semiconductor field-effect transistors (MOSFET).

### Claim 18 (depends on 10)

The semiconductor die of claim 10, wherein the logic circuit includes an AND logic gate and an NAND logic gate.

### Claim 19

A method of detecting a crack in a semiconductor die, comprising:
setting the CDU to a normal mode, wherein no operating voltage is applied to a metal pattern of the CDU, and the metal pattern is disposed in the semiconductor die;
setting the CDU to a crack detection mode, wherein the operating voltage is applied to the metal pattern of the CDU; and
determining whether a crack is in the semiconductor die based on an output of the CDU,
wherein the semiconductor die is connected to a second semiconductor die, the second semiconductor die includes a second metal pattern, and the method further comprising determining whether a crack is in the metal pattern, the second metal pattern, or a connection between the semiconductor die and the second semiconductor die.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
the CDU comprises a PMOS, an AND logic gate and an NAND logic gate,
the logic circuit includes a first external input and a second external input,
the AND logic gate generates a first output to a gate electrode of the PMOS based on the first external input and the output of the CDU, and
the NAND logic gate generates a second output to the output of the CDU based on the second external input and a voltage at a drain electrode of the PMOS.