# US 12,111,261 B2 · Integrated photodetector with direct binning pixel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,111,261 B2 - Document ID: US12111261B2 - Status: Granted - Kind: B2 - Application number: 18/330,295 - Filed: 2023-06-06 - Published: 2024-01-18 - Granted: 2024-10-08 - Earliest claimed: 2016-12-22 - Assignees: Quantum-Si Incorporated - Applicants: Quantum-Si Incorporated - Inventors: Jonathan M. Rothberg; Keith G. Fife; David M. Boisvert - Web page: https://patentgrep.com/patent/US12111261B2 ## CPC - G01N 21/6428: {Measuring fluorescence of fluorescent products of reactions or of fluorochrome labelled reactive substances, e.g. measuring quenching effects, using measuring "optrodes" (in vivo A61B5/00; immunoassay G01N33/53)} - C12Q 1/6869: Methods for sequencing - G01N 21/64: Fluorescence; Phosphorescence - G01N 21/6408: {with measurement of decay time, time resolved fluorescence} - G01N 21/6454: {using an integrated detector array} - G01S 7/4865: Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak (peak detection in noise, signal conditioning G01S7/487) - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H10F 39/014: {of CMOS image sensors} - H10F 39/026: {Wafer-level processing} - H10F 39/151: {Geometry or disposition of pixel elements, address lines or gate electrodes} - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes} - H10F 39/8037: {the integrated elements comprising a transistor} - G01N 21/6458: {Fluorescence microscopy (fluorescence microscopes per se G02B21/0076 and G02B21/16)} - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) - C12Q: MEASURING OR TESTING PROCESSES INVOLVING ENZYMES, NUCLEIC ACIDS OR MICROORGANISMS (immunoassay G01N33/53); COMPOSITIONS OR TEST PAPERS THEREFOR; PROCESSES OF PREPARING SUCH COMPOSITIONS; CONDITION-RESPONSIVE CONTROL IN MICROBIOLOGICAL OR ENZYMOLOGICAL PROCESSES - G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced. ## Claims ### Claim 1 An integrated circuit, comprising: a photodetection region configured to receive incident photons, the photodetection region being configured to produce a plurality of charge carriers in response to the incident photons; a first charge carrier storage region and a second charge carrier storage region on a same side of the photodetection region as the first charge carrier storage region; and at least one electrode comprising a first electrode, the first electrode located, at least in part, at a boundary of the photodetection region and the first charge carrier storage region to form a potential barrier between the photodetection region and the first charge carrier storage region, wherein the integrated circuit is controllable to: aggregate, in the first charge carrier storage region, charge carriers at least in part by lowering the potential barrier formed by the first electrode to allow charge carrier transfer from the photodetection region to the first charge carrier storage region, the charge carriers produced by the photodetection region in response to a plurality of excitation light pulses; read out a signal representative of a quantity of the charge carriers; and store, in the first charge carrier storage region and in the second charge carrier storage region, respectively, charge carriers received at different times with respect to trigger events. ### Claim 2 (depends on 1) The integrated circuit of claim 1, further comprising: a rejection region, wherein the at least one electrode further comprises a second electrode located, at least in part, at a boundary of the photodetection region and the rejection region to form a potential barrier between the photodetection region and the rejection region. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the integrated circuit is controllable to lower the potential barrier between the photodetection region and the rejection region while the potential barrier between the photodetection region and the first charge carrier storage region is raised and to lower the potential barrier between the photodetection region and the first charge carrier storage region while the potential barrier between the photodetection region and the rejection region is raised. ### Claim 4 (depends on 1) The integrated circuit of claim 1, further comprising: a semiconductor region located at the boundary of the photodetection region and the first charge carrier storage region, wherein the first electrode is positioned proximate the semiconductor region to control the potential barrier in the semiconductor region. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the integrated circuit is controllable to: aggregate charge carriers in the first charge carrier storage region received in one time period following a trigger event, and aggregate charge carriers in the second charge carrier storage region received in a later time period with respect to a trigger event. ### Claim 6 (depends on 1) The integrated circuit of claim 1, further comprising a readout node comprising a floating diffusion region configured to convert the charge carriers into a voltage to be read out as the signal representative of the quantity of the charge carriers. ### Claim 7 A system, comprising: an integrated circuit, comprising a pixel, the pixel comprising: a photodetection region configured to receive incident photons, the photodetection region being configured to produce a plurality of charge carriers in response to the incident photons; a first charge carrier storage region; a second charge carrier storage region; and at least one electrode comprising a first electrode, the first electrode located, at least in part, at a boundary of the photodetection region and the first charge carrier storage region to form a potential barrier between the photodetection region and the first charge carrier storage region; and wherein the system comprises a control circuit configured to control the pixel to: aggregate, in the first charge carrier storage region, charge carriers at least in part by controlling a voltage of the first electrode to lower the potential barrier to allow charge carrier transfer from the photodetection region to the first charge carrier storage region, the charge carriers produced by the photodetection region in response to a plurality of excitation light pulses; read out a signal representative of a quantity of the charge carriers; store, in the first charge carrier storage region and in the second charge carrier storage region, respectively, charge carriers received at different times with respect to trigger events; and lower the potential barrier formed by the first electrode following each of the trigger events. ### Claim 8 (depends on 7) The system of claim 7, wherein: the pixel further comprises a rejection region, and the at least one electrode further comprises a second electrode located, at least in part, at a boundary of the photodetection region and the rejection region to form a potential barrier between the photodetection region and the rejection region. ### Claim 9 (depends on 8) The system of claim 8, wherein the control circuit is configured to control the pixel to: lower the potential barrier between the photodetection region and the rejection region while the potential barrier between the photodetection region and the first charge carrier storage region is raised; and lower the potential barrier between the photodetection region and the first charge carrier storage region while the potential barrier between the photodetection region and the rejection region is raised. ### Claim 10 (depends on 7) The system of claim 7, wherein: the pixel further comprises a semiconductor region located at the boundary of the photodetection region and the first charge carrier storage region, and the first electrode is positioned proximate the semiconductor region to control the potential barrier in the semiconductor region. ### Claim 11 (depends on 7) The system of claim 7, wherein the control circuit is configured to control the pixel to: aggregate charge carriers in the first charge carrier storage region received in one time period following a trigger event, and aggregate charge carriers in the second charge carrier storage region received in a later time period with respect to a trigger event. ### Claim 12 (depends on 7) The system of claim 7, wherein the pixel further comprises a readout node comprising a floating diffusion region configured to convert the charge carriers into a voltage to be read out as the signal representative of the quantity of the charge carriers. ### Claim 13 A method, comprising: aggregating, in a first charge carrier storage region of at least one charge carrier storage region of a pixel, charge carriers at least in part by controlling a voltage of a first electrode of at least one electrode to lower a potential barrier to allow charge carrier transfer from a photodetection region of the pixel to the first charge carrier storage region, the first electrode located, at least in part, at a boundary of the photodetection region and the first charge carrier storage region, and the charge carriers produced by the photodetection region in response to a plurality of excitation light pulses; reading out a signal representative of a quantity of the charge carriers; and storing, in the first charge carrier storage region and in a second charge carrier storage region of the at least one charge carrier storage region, respectively, charge carriers received at different times with respect to trigger events, wherein the potential barrier formed by the first electrode is lowered following each of the trigger events. ### Claim 14 (depends on 13) The method of claim 13, further comprising: controlling a voltage of a second electrode of the at least one electrode to lower a potential barrier to draw charge carriers from the photodetection region to a rejection region, wherein the second electrode is located, at least in part, at a boundary of the photodetection region and the rejection region. ### Claim 15 (depends on 14) The method of claim 14, further comprising: lowering the potential barrier between the photodetection region and the rejection region while the potential barrier between the photodetection region and the first charge carrier storage region is raised; and lowering the potential barrier between the photodetection region and the first charge carrier storage region while the potential barrier between the photodetection region and the rejection region is raised. ### Claim 16 (depends on 13) The method of claim 13, wherein the first electrode is positioned proximate a semiconductor region, located at the boundary of the photodetection region and the first charge carrier storage region, and controlling the voltage of the first electrode comprises controlling the potential barrier in the semiconductor region. ### Claim 17 (depends on 13) The method of claim 13, wherein storing charge carriers received at different times with respect to trigger events comprises: aggregating charge carriers in the first charge carrier storage region received in one time period following a trigger event, and aggregating charge carriers in the second charge carrier storage region received in a later time period with respect to a trigger event. ### Claim 18 An integrated circuit, comprising: a photodetection region configured to receive incident photons, the photodetection region being configured to produce a plurality of charge carriers in response to the incident photons; a first charge carrier storage region; a second charge carrier storage region; a readout region configured to receive charge carriers from each of the first charge carrier storage region and the second charge carrier storage region; and at least one electrode comprising a first electrode, the first electrode located, at least in part, at a boundary of the photodetection region and the first charge carrier storage region to form a potential barrier between the photodetection region and the first charge carrier storage region, wherein the integrated circuit is controllable to: aggregate, in the first charge carrier storage region, charge carriers at least in part by lowering the potential barrier formed by the first electrode to allow charge carrier transfer from the photodetection region to the first charge carrier storage region, the charge carriers produced by the photodetection region in response to a plurality of excitation light pulses; read out a signal representative of a quantity of the charge carriers; store, in the first charge carrier storage region and in the second charge carrier storage region, respectively, charge carriers received at different times with respect to trigger events; and lower the potential barrier formed by the first electrode following each of the trigger events. ### Claim 19 (depends on 18) The integrated circuit of claim 18, further comprising: a rejection region, wherein the at least one electrode further comprises a second electrode located, at least in part, at a boundary of the photodetection region and the rejection region to form a potential barrier between the photodetection region and the rejection region. ### Claim 20 (depends on 19) The integrated circuit of claim 19, wherein the integrated circuit is controllable to lower the potential barrier between the photodetection region and the rejection region while the potential barrier between the photodetection region and the first charge carrier storage region is raised and to lower the potential barrier between the photodetection region and the first charge carrier storage region while the potential barrier between the photodetection region and the rejection region is raised. ### Claim 21 (depends on 18) The integrated circuit of claim 18, further comprising: a semiconductor region located at the boundary of the photodetection region and the first charge carrier storage region, wherein the first electrode is positioned proximate the semiconductor region to control the potential barrier in the semiconductor region. ### Claim 22 (depends on 18) The integrated circuit of claim 18, wherein the integrated circuit is controllable to: aggregate charge carriers in the first charge carrier storage region received in one time period following a trigger event, and aggregate charge carriers in the second charge carrier storage region received in a later time period with respect to a trigger event.