Differential to single ended pipeline analog to digital converter
AssigneeDunmore Circuits, LLC
InventorLarry L. Harris
Life of this patent
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Abstract
A pipeline analog to digital converter includes a “k” number of stages and an output data register. A first stage of the “k” number of stages is configured to receive an analog differential input signal and produce a first digital output and a first single ended analog output. A second stage of the “k” number of stages is configured to receive the first single ended analog output and produce a second digital output. The output data register is configured to generate an output digital value based on the first and second digital outputs.
Claims20
A pipeline analog to digital converter (ADC) comprising:
- a first stage of a “k” number of stages, wherein the first stage is configured to receive an analog differential input signal and produce a first digital output and a first single ended analog output, and wherein the first stage includes a differential input sample and hold circuit comprising:
- a switched capacitor configured to sample, during a first time period, the analog differential input signal to produce a sampled analog differential input signal;
- and
- an operational amplifier configured to, during a second time period, generate a single ended voltage signal based on a voltage difference between the sampled analog differential input signal and a common voltage, wherein the single ended voltage signal is output on a single ended output line of the operational amplifier;
- a second stage of the “k” number of stages is configured to receive the first single ended analog output and produce a second digital output;
- and
- an output data register that is configured to generate an output digital value based on the first and second digital outputs.
A pipeline analog to digital converter (ADC) comprising:
- a first stage of a “k” number of stages, wherein the first stage is configured to receive an analog differential input signal and produce a first digital output and a first single ended analog output, and wherein the first stage includes a pseudo differential input sample and hold circuit comprising:
- a feedback capacitor;
- a sampling capacitor operable to sample, during a first time period, the analog differential input signal to produce a sampled analog differential input signal;
- a charge subtraction capacitor operable to subtract a charge from the sampled analog differential input signal to produce a subtracted sampled analog differential input signal;
- and
- an operational amplifier operable to, during a second time period, generate a single ended voltage signal based on a voltage difference between the subtracted sampled analog differential input signal and a common voltage, wherein the single ended voltage signal is output on a single ended output line of the operational amplifier;
- a second stage of the “k” number of stages configured to receive the first single ended analog output and produce a second digital output;
- and
- an output data register configured to generate an output digital value based on the first digital output.
Dependencies are inferred from the claim text.