Single sideband mixer
AssigneeRealtek Semiconductor Corp.
InventorChia-Liang (Leon) Lin
Life of this patent
Estimating the term…
Abstract
A SSB (single sideband) mixer is configured to mix a first signal with a second signal, both the first signal and the second signal being a four-phase signal, and comprises eight gated inverters, each receiving a respective phase of the first signal and conditionally outputting a respective current in accordance with a control of a respective phase of the second signal, wherein currents output from the eight gated inverters are summed to establish a third signal that is a two-phase signal.
Claims10
A SSB (single sideband) mixer configured to mix a first signal with a second signal, both the first signal and the second signal being a four-phase signal, and comprising:
- a first GI (gated inverter) configured to receive a first phase of the first signal and conditionally output a first current to a first node when a first phase of the second signal is asserted;
- a second GI configured to receive a third phase of the first signal and conditionally output a second current to the first node when a third phase of the second signal is asserted;
- a third GI configured to receive a second phase of the first signal and conditionally output a third current to the first node when a fourth phase of the second signal is asserted;
- a fourth GI configured to receive a fourth phase of the first signal and conditionally output a fourth current to the first node when a second phase of the second signal is asserted;
- a fifth GI configured to receive the first phase of the first signal and conditionally output a fifth current to a second node when the third phase of the second signal is asserted;
- a sixth GI configured to receive the third phase of the first signal and conditionally output a sixth current to the second node when the first phase of the second signal is asserted;
- a seventh GI configured to receive the second phase of the first signal and conditionally output a seventh current to the second node when the second phase of the second signal is asserted;
- and
- an eighth GI configured to receive the fourth phase of the first signal and conditionally output an eighth current to the second node when the fourth phase of the second signal is asserted,
- wherein the GI circuit comprises:
- a first NMOST (n-channel metal oxide semiconductor transistor), of which a source, a gate, and a drain connect to the ground pin, the complementary control pin, and a first gate node, respectively;
- a first PMOST (p-channel metal oxide semiconductor transistor), of which a source, a gate, and a drain connect to the input pin, the complementary control pin, and the first gate node, respectively;
- a second NMOST, of which a source, a gate, and a drain connect to the input pin, the control pin, and a second gate node, respectively;
- a second PMOST, of which a source, a gate, and a drain connect to the power pin, the control pin, and the second gate node, respectively;
- a third NMOST, of which a source, a gate, and a drain connect to the ground pin, the first gate node, and the output pin, respectively;
- and a third PMOST, of which a source, a gate, and a drain connect to the power pin, the second gate node, and the output pin, respectively.
A GI (gated inverter) configured to receive a phase of a first signal via an input pin, receive a phase of a second signal via a control pin, receive a complementary phase of the second signal that is complementary to said phase of the second signal via a complementary control pin, and output a current to an output node via an output pin, wherein the GI comprises:
- a first NMOST (n-channel metal oxide semiconductor transistor), of which a source, a gate, and a drain connect to a ground pin, the complementary control pin, and a first gate node, respectively;
- a first PMOST (p-channel metal oxide semiconductor transistor), of which a source, a gate, and a drain connect to the input pin, the complementary control pin, and the first gate node, respectively;
- a second NMOST, of which a source, a gate, and a drain connect to the input pin, the control pin, and a second gate node, respectively;
- a second PMOST, of which a source, a gate, and a drain connect to a power pin, the control pin, and the second gate node, respectively;
- a third NMOST, of which a source, a gate, and a drain connect to the ground pin, the first gate node, and the output pin, respectively;
- and
- a third PMOST, of which a source, a gate, and a drain connect to the power pin, the second gate node, and the output pin, respectively.
Dependencies are inferred from the claim text.