Back to results
US 12,107,150 B2Granted
Electroless plating method for metal gate fill
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Yi Lee, Chi On Chui
Life of this patent
Estimating the term…
Abstract
Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.
Claims20
A method comprising:
- etching a dummy gate over a channel nanostructure to remove the dummy gate and form a first opening revealing the channel nanostructure;
- etching a dummy nanostructure abutting the channel nanostructure to remove the dummy nanostructure and expose a surface of the channel nanostructure;
- depositing a first dielectric layer in the first opening, the first dielectric layer surrounding the channel nanostructure;
- and
- providing an aqueous plating solution to the first opening to plate a metal into the first opening, the metal filling up the first opening, the aqueous plating solution comprising suppressors, wherein the suppressors are more densely distributed at sidewalls of the first opening than at a bottom of the first opening during plating the metal.
2 more elements
A method comprising:
- depositing epitaxial source/drain regions in a fin recess on either side of a gate;
- removing a dummy gate structure between two gate spacers of the gate to form an opening between the two gate spacers;
- depositing a first gate dielectric layer in the opening, the first gate dielectric layer covering a channel region of the gate;
- and
- chemically plating a conductive fill in the opening, at a plating rate which is 10 to 25 times greater at a bottom of the opening than at sides of the opening.
2 more elements
A method comprising:
- removing a dummy gate to form a recess exposing a nanostructure channel region, wherein a height to width ratio of the recess is between 10:1 and 20:1;
- depositing a gate dielectric layer on the nanostructure channel region;
- and
- depositing a gate electrode on the gate dielectric layer, wherein depositing the gate electrode comprises:
- providing a plating solution into the recess, the plating solution including chemical accelerators and chemical suppressors, and
- reducing a metal from the plating solution to deposit the metal in the recess.
3 more elements
Dependencies are inferred from the claim text.