Batching aware techniques for refreshing memory devices
AssigneeQUALCOMM Incorporated
InventorsSaurabh Sethi, Madhukar Reddy N, Vasantha Kumar Bandur Puttappa, Amulya Srinivasan Margasahayam
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Abstract
Aspects of the present disclosure are directed to techniques and procedures for reducing memory (e.g., DRAM) access latency (e.g., read latency, write latency) due to memory refreshes. In some aspects, a memory refresh scheduling algorithm can take into account of memory access batching (e.g., read batch, write batch). In some aspects, a refresh scheduling algorithm can schedule more or prioritize refreshes to occur during a write batch to reduce memory read access latency because fewer refreshes are scheduled during memory read access. The techniques can be adapted to reduce write latency.
Claims28
An apparatus for data storage, comprising:
- a memory device comprising a plurality of memory banks;
- and
- a memory controller coupled to the memory device, the memory controller being configured to:
- perform one or more read batches to the memory device, each read batch comprising a plurality of read commands configured to read data from the memory device;
- perform one or more write batches to the memory device, each write batch comprising a plurality of write commands configured to write data to the memory device;
- and
- perform a plurality of refreshes to the plurality of memory banks within a refresh interval, a first portion of the plurality of refreshes being scheduled to occur during the one or more write batches, and a second portion of the plurality of refreshes being scheduled to occur during the one or more read batches, a ratio of an average number of refreshes included in the second portion to an average number of refreshes included in the first portion, being less than one.
A method of operating a memory device, comprising:
- performing one or more read batches to the memory device, each read batch comprising a plurality of read commands configured to read data from the memory device;
- performing one or more write batches to the memory device, each write batch comprising a plurality of write commands configured to write data to the memory device;
- and
- performing a plurality of refreshes to a plurality of memory banks of the memory device within a refresh interval, a first portion of the plurality of refreshes being scheduled to occur during the one or more write batches, and a second portion of the plurality of refreshes being scheduled to occur during the one or more read batches, a ratio of an average number of refreshes included in the second portion to an average number of refreshes included in the first portion, being less than one.
An apparatus for data storage, comprising:
- a memory device comprising a plurality of memory banks;
- and
- a memory controller coupled to the memory device, the memory controller being configured to:
- perform one or more read batches to the memory device, each read batch comprising a plurality of read commands configured to read data from the memory device;
- perform one or more write batches to the memory device, each write batch comprising a plurality of write commands configured to write data to the memory device;
- and
- perform a plurality of refreshes to the plurality of memory banks within a refresh interval, a first portion of the plurality of refreshes being scheduled to occur during the one or more write batches, and a second portion of the plurality of refreshes being scheduled to occur during the one or more read batches, a ratio of an average number of refreshes included in the first portion to an average number of refreshes included in the second portion, being less than one.
A method of operating a memory device, comprising:
- performing one or more read batches to the memory device, each read batch comprising a plurality of read commands configured to read data from the memory device;
- performing one or more write batches to the memory device, each write batch comprising a plurality of write commands configured to write data to the memory device;
- and
- performing a plurality of refreshes to a plurality of memory banks of the memory device within a refresh interval, a first portion of the plurality of refreshes being scheduled to occur during the one or more write batches, and a second portion of the plurality of refreshes being scheduled to occur during the one or more read batches, a ratio of an average number of refreshes included in the first portion to an average number of refreshes included in the second portion, being less than one.
Dependencies are inferred from the claim text.