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US 12,103,303 B2Granted
Fluid ejection devices including a memory
AssigneeHewlett-Packard Development Company, L.P.
InventorBoon Bing Ng
Life of this patent
Estimating the term…
Abstract
An integrated circuit to drive a plurality of fluid actuation devices includes a fire line, a plurality of memory elements, a first switch, and a plurality of second switches. The first switch is electrically coupled between the fire line and a first side of each memory element of the plurality of memory elements. Each second switch is electrically coupled to a second side of a respective memory element of the plurality of memory elements.
Claims13
An integrated circuit comprising:
- a first memory;
- a second memory comprising a plurality of memory elements;
- a first control line to access the second memory for read and/or write operations when the second memory is enabled;
- a first switch electrically coupled between the first control line and a first side of each memory element of the plurality of memory elements;
- a plurality of second switches, each second switch electrically coupled to a second side of a respective memory element of the plurality of memory elements;
- an ID line electrically coupled to the first memory;
- a buffer having an input coupled with the ID line and an output coupled with the first switch via a first signal node, the first signal node coupling the output of the buffer to the gate of the first switch;
- and
- an inverter having an input coupled with the ID line and an output coupled with a third switch via a second signal node, the third switch coupled with at least one of the plurality of second switches,
- wherein the second memory is to be accessed for at least one of the read and/or write operations through a second control line via a first transistor coupled to a second side of the respective memory element of the plurality of memory elements, and wherein a gate of the first transistor is coupled to at least one of the plurality of second switches via a second transistor, and
- wherein the second memory is enabled via the buffer and the inverter in response to a first logic level on the ID line.
8 more elements
An integrated circuit comprising:
- a first control line;
- a first memory;
- a second memory comprising a plurality of memory elements;
- a first transistor having a source-drain path electrically coupled between the first control line and a first side of each memory element of the plurality of memory elements;
- a plurality of second transistors, each second transistor having a source-drain path electrically coupled between a respective memory element of the plurality of memory elements and a common node;
- an ID line electrically coupled to the first memory;
- a buffer having an input coupled with the ID line and an output coupled with the first transistor via a first signal node, the first signal node coupling the output of the buffer to the gate of the first switch;
- and
- an inverter having an input coupled with the ID line and an output coupled with a third transistor via a second signal node, the third transistor coupled with at least one of the plurality of second transistors,
- wherein the second memory is to be accessed for a read or write operation through the second control line via the first transistor coupled to a second side of the respective memory element of the plurality of memory elements, and wherein a gate of the first transistor is coupled to at least one of the plurality of second transistors via a fourth transistor, and
- wherein the second memory is enabled via the buffer and the inverter in response to a first logic level on the ID line.
8 more elements
Dependencies are inferred from the claim text.