Microelectronic devices, and related memory devices and electronic systems

A microelectronic device, comprising:

• a first memory array region comprising first vertically extending strings of memory cells;
• first digit lines coupled to the first vertically extending strings of memory cells;
• a second memory array region comprising second vertically extending strings of memory cells;
• second digit lines coupled to the second vertically extending strings of memory cells;
• an additional region horizontally interposed between the first memory array region and the second memory array region and comprising multiplexer devices coupled to the first digit lines and the second digit lines, each of the multiplexer devices comprising:
• a pillar structure vertically extending through select gate structures;
• and
• a pillar contact structure on the pillar structure and coupled to one of the first digit lines or one of the second digit lines;
• and
• page buffer devices coupled to the multiplexer devices.

A memory device, comprising:

• a stack structure comprising:
• a first region comprising access line structures;
• and
• a second region vertically overlying the first region and comprising select gate structures;
• first strings of memory cells vertically extending through the stack structure;
• second strings of memory cells vertically extending through the stack structure;
• first digit line structures coupled to the first strings of memory cells;
• second digit line structures coupled to the second strings of memory cells;
• multiplexer devices horizontally interposed between the first strings of memory cells and the second strings of memory cells, the multiplexer devices coupled to the select gate structures of the stack structure, the first digit line structures, and the second digit line structures;
• and
• a base structure vertically underlying the stack structure and comprising a logic region including page buffer devices coupled to the multiplexer devices.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably connected to the input device and the output device;
• and
• a memory device operably connected to the processor device and comprising:
• a stack structure including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure comprises:
• a first region comprising a lower group of the conductive structures configured as access line structures;
• and
• a second region overlying the first region and comprising an upper group of the conductive structures configured as select gate structures;
• strings of memory cells vertically extending through the stack structure;
• first digit lines vertically overlying the stack structure and coupled to some of the strings of memory cells;
• second digit lines vertically overlying the stack structure and coupled to some other of the strings of memory cells;
• multiplexer devices coupled to the first digit lines, the second digit lines, and the upper group of the conductive structures within the second region of the stack structure;
• and
• a base structure vertically underlying the stack structure and comprising logic circuitry including page buffer devices coupled to the multiplexer devices.