Fast frequency hopping of modulated signals

A method, comprising:

• generating data program signals to program a Phase-Locked Loop Waveform Generator (PLLWG) and generating a trigger command signal instructing the PLLWG to generate an analog tuning signal, the generating of the data communication signals and the generating of the trigger command signal being performed by a processor;
• generating, by the PLLWG coupled to the processor, the analog tuning signal based on the trigger command signal;
• receiving the analog tuning signal, amplifying the analog tuning signal, and generating a control voltage, the receiving of the analog tuning signal, the amplifying of the analog tuning signal, and the generating the control voltage being performed by an amplifier circuit;
• receiving the control voltage and amplifying the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal, the receiving of the control voltage and the amplifying of the control voltage being performed by a Voltage Controlled Oscillator (VCO) coupled to the amplifier circuit;
• providing a timing resource, the timing source generating a processor timing signal for the processor and a PLLWG timing signal for the PLLWG;
• wherein the timing resource comprises at least one Asynchronous Clock Generator (ACG), wherein the step of timing source generating comprises the step of timing source generating at least one of the processor timing signal and the PLLWG timing signal by the at least one ACG;
• and
• wherein the at least one ACG comprises a first ACG and a second ACG, wherein the step of timing source generating comprises the step of timing source generating the processor timing signal with the first ACG, and the step of timing source generating the PLLWG timing signal by a second ACG.

A method, comprising:

• generating data program signals to program a Phase-Locked Loop Waveform Generator (PLLWG) and generating a trigger command signal instructing the PLLWG to generate an analog tuning signal, the generating of the data communication signals and the generating of the trigger command signal being performed by a processor;
• generating, by the PLLWG coupled to the processor, the analog tuning signal based on the trigger command signal;
• receiving the analog tuning signal, amplifying the analog tuning signal, and generating a control voltage, the receiving of the analog tuning signal, the amplifying of the analog tuning signal, and the generating the control voltage being performed by an amplifier circuit;
• receiving the control voltage and amplifying the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal, the receiving of the control voltage and the amplifying of the control voltage being performed by a Voltage Controlled Oscillator (VCO) coupled to the amplifier circuit;
• providing a timing resource, the timing source generating a processor timing signal for the processor and a PLLWG timing signal for the PLLWG
• generating, by the processor, a data command which instructs a Digital-to-Analog Converter (DAC) to generate an in-phase modulation signal and a QM signal;
• and
• receiving, by an upconverting QM mixer, the in-phase modulation signal, the QM signal, and the amplified RF channel frequency signal;
• and
• generating, by the upconverting QM mixer, a modulated radio frequency output based on the in-phase modulation signal, the QM signal, and the amplified RF channel frequency signal.