Semiconductor integrated circuit and methodology for making same

An integrated circuit comprising:

• a plurality of semiconductor layers supported on a substrate, wherein the plurality of semiconductor layers includes i) at least one n-type layer, ii) an inverted p-type modulation doped quantum well structure formed above the at least one n-type layer, wherein the inverted p-type modulation doped quantum well structure includes at least one pair of quantum well layer and barrier layer disposed above a p-type charge sheet, iii) a non-inverted n-type modulation doped quantum well structure formed above the inverted p-type modulation doped quantum well structure, wherein the non-inverted n-type modulation doped quantum well structure includes an n-type charge sheet disposed above least one pair of quantum well layer and barrier layer, and iv) at least one p-type layer disposed above the non-inverted n-type modulation doped quantum well structure, wherein the at least one p-type layer includes a first p-type layer of a first concentration of p-type doping formed below a second p-type layer of a second concentration of p-type doping, wherein the first concentration of p-type doping of the first p-type layer is greater than the second concentration of p-type doping of the second p-type layer;
• a p-type gate implanted region in contact with the first p-type layer;
• an n-type source ion implanted region and an n-type drain ion implanted region which are both in contact with the non-inverted n-type modulation doped quantum well structure;
• a gate electrode of a n-channel HFET device in contact with the p-type gate ion implanted region;
• and
• source and drain electrodes of the n-channel HFET device in contact with the n-type source ion implanted region and the n-type drain ion implanted region, respectively.