Memory device and erasing and verification method thereof
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsKaiwei Li, Jianquan Jia, Hongtao Liu, An Zhang
Life of this patent
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Abstract
A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.
Claims20
A memory device, comprising:
- a memory string comprising a top select gate, word lines, and a bottom select gate;
- and
- a control circuit coupled to the memory string and configured to, in an erasing operation:
- apply an erasing voltage to the memory string;
- apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string;
- apply a first turn-on voltage to the bottom select gate before applying the verifying voltage to the at least one word line;
- and
- apply a second turn-on voltage to the top select gate after stopping application of the erasing voltage for a period of time.
A method for operating a memory device comprising a memory string, the memory string comprising a top select gate, word lines, and a bottom select gate, the method comprising:
- applying an erasing voltage to the memory string;
- applying a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string;
- applying a first turn-on voltage to the bottom select gate before applying the verifying voltage to the at least one word line;
- and
- applying a second turn-on voltage to the top select gate after stopping application of the erasing voltage for a period of time.
A memory system, comprising:
- a memory device comprising:
- a memory string comprising a top select gate, word lines, and a bottom select gate;
- and
- a control circuit coupled to the memory string and configured to, in an erasing operation:
- apply an erasing voltage to the memory string;
- apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string;
- apply a first turn-on voltage to the bottom select gate before applying the verifying voltage to the at least one word line;
- and
- apply a second turn-on voltage to the top select gate after stopping application of the erasing voltage for a period of time.
Dependencies are inferred from the claim text.