Systems and methods for quarter rate serialization

A serializer based on quarter rate architecture for a transmitter comprising:

• a port configured to receive a quarter rate data input;
• a quarter-phase clock generator configured to generate an in-phase clock signal, a complementary in-phase clock signal, and quarter-phase clock signal, and a complementary quarter-phase clock signal;
• and
• a plurality of branches configured to receive the quarter rate data input, and to sequentially output data based on a clock signal generated by the quarter-phase clock generator, each of the plurality of branches including,
• a first logical gate configured to receive at least one data input among the quarter rate data input and to output a first logical output based on (A) one of the in-phase clock signal or the complementary in-phase clock signal and on (B) one of the quarter-phase clock signal or the complementary quarter-phase clock signal,
• a second logical gate configured to receive the at least one data input and to output a second logical output based on (C) the other of the in-phase clock signal or the complementary in-phase clock signal and on (D) the other of the quarter-phase clock signal or the complementary quarter-phase clock signal, and
• driver circuitry connected to an output of the first logical gate and an output of the second logical gate, the driver circuitry configured to output a final logical output, the final logical output associated with each branch of the plurality of branches,
• wherein the main data input corresponds to a second latch output of a final stage flop of a previous serializer stage within the transmitter.

A method, implemented in a serializer for quarter rate serialization, comprising:

• receiving a plurality of clock signals including an in-phase clock signal, a complementary in-phase clock signal, a quarter-phase clock signal and a complementary quarter-phase clock signals, the plurality of clock signals defining a quarter-phase clock;
• receiving, at one of a plurality of branches, each including at least one NAND gate and at least one NOR gate, a quarter rate data input;
• sequentially outputting data in accordance with the plurality of clock signals;
• receiving, by a first logical gate in each branch of the plurality of branches, at least one data input amongst the quarter rate data input, one of the in-phase clock signal or the complementary in-phase clock signal, and one of the quarter-phase clock signal or the complementary quarter phase clock signal;
• outputting a first logical output based on the received one of the in-phase clock signal or the complementary in-phase clock signal and on the received one of the quarter-phase clock signal or the complementary quarter-phase clock signal;
• receiving, by a second logical gate in each branch, the at least one data input, the another one of the received in-phase clock signal or the complementary in-phase clock signal, and the another one of the received quarter-phase clock signal or the complementary quarter-phase clock signal;
• outputting a second logical output based on the another one of the in-phase clock signal or the complementary in-phase clock signal and on the another one of the quarter-phase clock signal or the complementary quarter-phase clock signal;
• and
• outputting, by driver circuitry connected at an output of the first logical gate and the second logical gate a final logical output associated with the one of the plurality of branches.